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Buffer block planning for interconnect-driven floorplanning

Authors:

David Zhigang PanAuthors Info & Claims

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Pages 358 - 363

Published: 07 November 1999 Publication History

Abstract

This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.

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Cited By

Chen XHuang XXiang YZhang DRanjan RLiao C(2017)A CPS framework based perturbation constrained buffer planning approach in VLSI designJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.11.013103:C(3-10)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.11.013
Ahmed MMohapatra SChrzanowska-Jeske MTaskin BHo T(2016)Buffered Interconnects in 3D IC Layout DesignProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947366(1-8)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947366
He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
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Index Terms

Buffer block planning for interconnect-driven floorplanning

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cover image ACM Conferences

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

November 1999

613 pages

ISBN:0780358325

Sponsors

IEEE-EDS: Electronic Devices Society
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

Publisher

IEEE Press

Publication History

Published: 07 November 1999

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ICCAD '99

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IEEE-EDS
SIGDA
IEEE-CAS
IEEE-CS

ICCAD '99: The International Conference on Computer Aided Design.

November 7 - 11, 1999

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Chen XHuang XXiang YZhang DRanjan RLiao C(2017)A CPS framework based perturbation constrained buffer planning approach in VLSI designJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.11.013103:C(3-10)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.11.013
Ahmed MMohapatra SChrzanowska-Jeske MTaskin BHo T(2016)Buffered Interconnects in 3D IC Layout DesignProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947366(1-8)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947366
He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
Hu SLi ZAlpert C(2009)A fully polynomial time approximation scheme for timing driven minimum cost buffer insertionProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630026(424-429)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630026
Dong QYang BLi JNakatake SLombardi FBhanja SMassoud YBahar R(2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531636
Akl CBayoumi MNarayanan VYan ZMacii EBhanja S(2008)Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater countProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366187(327-332)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366187
Akl CBayoumi M(2008)Reducing interconnect delay uncertainty via hybrid polarity repeater insertionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200086116:9(1230-1239)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000861
He ODong SBian JMa YHong XZhou HMacii EYan ZMassoud Y(2007)An effective buffer planning algorithm for IP based fixed-outline SOC placementProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228917(564-569)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228917
Jahanian AZamani MZhou HMacii EYan ZMassoud Y(2007)Improved timing closure by early buffer planning in floor-placement design flowProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228916(558-563)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228916
Zhang TSapatnekar S(2007)Simultaneous shield and buffer insertion for crosstalk noise reduction in global routingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89864115:6(624-636)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898641
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