Article

Free access

Buffer block planning for interconnect-driven floorplanning

Authors:

David Zhigang PanAuthors Info & Claims

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Pages 358 - 363

Published: 07 November 1999 Publication History

Abstract

This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.

References

[1]

J. Cong, L. He, C.-K. Koh, and R H. Madden, "Performance optimization of VLSI interconnect layout," Integration, the VLSI Journal, vol. 21, pp. 1-94, 1996.

Digital Library

[2]

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.

[3]

R. Otten, "Global wires harmful?," in Proc. Int. Syrup. on Physical Design, pp. 104-109, Apr. 1998.

Digital Library

[4]

J. Cong and D. Z. Pan, "Interconnect delay estimation models for synthesis and design planning," in Proc. Asia and South Pacific Design Automation Conf., pp. 97-100, Jan., 1999.

[5]

J. Cong, L. He, K.-Y. Khoo, C.-K. Koh, and D. Z. Pan, "Interconnect design for deep submicron ICs," in Proc. Int. Conf. on Computer Aided Design, pp. 478-485, 1997.

Digital Library

[6]

J. Cong, "Challenges and opportunities for design innovations in nanometer technologies.," in SRC Working Papers, http://www.src.org/prg_mgmt/frontier.dgw, Dec. 1997.

[7]

L. E E E van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 865-868, 1990.

[8]

J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," in Proc. Int. Conf. on Computer Aided Design, pp. 138-143, Nov. 1995.

Digital Library

[9]

T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," in Proc. Int. Conf. on Computer Aided Design, pp. 44-49, Nov. 1996.

Digital Library

[10]

C. C. N. Chu and D. F. Wong, "Closed form solution to simultaneous buffer insertion/sizing and wire sizing," in Proc. Int. Syrup. on Physical Design, pp. 192-197, 1997.

Digital Library

[11]

W. M. Dai, B. Eschermann, E. S. Kuh, and M. Pedram, "Hierachical placement and floorplanning for bear," in IEEE Trans. on Computer- Aided Design, pp. 1335-1349, 1989.

[12]

D. Wong and C. L. Liu, "Floorplan design of VLSI circuits," inAlgorithmica, pp. 263-291, 1989.

[13]

H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectanglepacking-based module placement," in Proc. of Int. Conf. on Computer- Aided Design, pp. 472-479, 1995.

Digital Library

[14]

M. Kang, W. Dai, T. Dillinger, and D. LaPotin, "Delay bounded buffered tree construction for timing driven floorplanning," in Proc. of lnt. Conf. on Computer-Aided Design, pp. 707-712, 1997.

Digital Library

[15]

J. Cong, "An interconnect-centric design flow for nanometer technologies," in Proc. of lnt' l Syrup. on VLSI Technology, Systems, and Applications, pp. 54-57, June, 1999.

[16]

J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnect-driven floorplanning," Tech. Rep. 990036, UCLA CS Dept, 1999.

[17]

Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997.

[18]

R. Otten, "Graphs in floor-plan design," International Journal of Circuit Theory and Applications, vol. 16, pp. 391-410, Oct. 1988.

[19]

"http://www.cbl.ncsu.edu/cbl_docs/lys92.html,"

[20]

C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. Design Automation Conf, 1997.

Digital Library

[21]

J. Cong, T. Kong, D. Xu, F. Liang, J. S. Liu, and W. H. Wong, "Relaxed simulated tempering for VLSI floorplan design," in Proc. Asia and South Pacific Design Automation Conf., pp. 13-16, Jan., 1999.

Cited By

Chen XHuang XXiang YZhang DRanjan RLiao C(2017)A CPS framework based perturbation constrained buffer planning approach in VLSI designJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.11.013103:C(3-10)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.11.013
Ahmed MMohapatra SChrzanowska-Jeske MTaskin BHo T(2016)Buffered Interconnects in 3D IC Layout DesignProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947366(1-8)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947366
He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
Show More Cited By

Index Terms

Buffer block planning for interconnect-driven floorplanning

Recommendations

Noise-aware buffer planning for interconnect-driven floorplanning
ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to ...
Routability driven floorplanner with buffer block planning
ISPD '02: Proceedings of the 2002 international symposium on Physical design

In traditional floorplanners, area minimization is an important issue. However, due to the recent advances in VLSI technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the ...
Routability-driven repeater block planning for interconnect-centric floorplanning

In this paper, we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and derive an analytical formula for their computation. We develop a routability-...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

November 1999

613 pages

ISBN:0780358325

Sponsors

IEEE-EDS: Electronic Devices Society
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

Publisher

IEEE Press

Publication History

Published: 07 November 1999

Check for updates

Qualifiers

Article

Conference

ICCAD '99

Sponsor:

IEEE-EDS
SIGDA
IEEE-CAS
IEEE-CS

ICCAD '99: The International Conference on Computer Aided Design.

November 7 - 11, 1999

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Upcoming Conference

ICCAD '24

Sponsor:
sigda

IEEE/ACM International Conference on Computer-Aided Design

October 27 - 31, 2024

New York , NY , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

59
Total Citations
View Citations
391
Total Downloads

Downloads (Last 12 months)33
Downloads (Last 6 weeks)7

Reflects downloads up to 16 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chen XHuang XXiang YZhang DRanjan RLiao C(2017)A CPS framework based perturbation constrained buffer planning approach in VLSI designJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.11.013103:C(3-10)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2016.11.013
Ahmed MMohapatra SChrzanowska-Jeske MTaskin BHo T(2016)Buffered Interconnects in 3D IC Layout DesignProceedings of the 18th System Level Interconnect Prediction Workshop10.1145/2947357.2947366(1-8)Online publication date: 4-Jun-2016
https://dl.acm.org/doi/10.1145/2947357.2947366
He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
Hu SLi ZAlpert C(2009)A fully polynomial time approximation scheme for timing driven minimum cost buffer insertionProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630026(424-429)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630026
Dong QYang BLi JNakatake SLombardi FBhanja SMassoud YBahar R(2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531636
Akl CBayoumi MNarayanan VYan ZMacii EBhanja S(2008)Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater countProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366187(327-332)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366187
Akl CBayoumi M(2008)Reducing interconnect delay uncertainty via hybrid polarity repeater insertionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200086116:9(1230-1239)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000861
He ODong SBian JMa YHong XZhou HMacii EYan ZMassoud Y(2007)An effective buffer planning algorithm for IP based fixed-outline SOC placementProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228917(564-569)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228917
Jahanian AZamani MZhou HMacii EYan ZMassoud Y(2007)Improved timing closure by early buffer planning in floor-placement design flowProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228916(558-563)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228916
Zhang TSapatnekar S(2007)Simultaneous shield and buffer insertion for crosstalk noise reduction in global routingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89864115:6(624-636)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898641
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents