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Design through transformation

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J. B. BendasAuthors Info & Claims

DAC '83: Proceedings of the 20th Design Automation Conference

Pages 253 - 256

Published: 27 June 1983 Publication History

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Abstract

The design and verification subsystem (DAV) within IBM's engineering design system (EDS) was developed to significantly increase logic designer productivity. To obtain this gain in productivity, emphasis was placed on creating a system environment which would encourage a structured approach towards design. A key component within DAV is the logic transformation subsystem (LTS). Using LTS, the designer can automatically synthesize and map a higher-level logic description into a design implementation under cost, performance, and technology constraints. This paper describes the various uses of transformation within a structured design context and provides details on the implementation of LTS.

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P. Horstmann, F. Rubin, "A Logic Entry Front-end for Improved Engineering Productivity," 20th Design Automation Conference, ACM and IEEE, Miami, Florida, 1983.

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D. Cheng, F. Magistro, C. Rimkus, M. Wayne, "Design Verification in a VLSI Design Environment: A Hierarchically Based Interactive Simulation System," 20th Design Automation Conference, ACM IEEE, Miami, Florida, 1983.

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Morgan VGregory DNewton A(1991)An ECL logic synthesis systemProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127637(106-111)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127637
Suzuki SBitoh TKakimoto MTakahashi KSugimoto T(1987)TRIP: an automated technology mapping systemProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37966(523-529)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37966
Saunders L(1987)The IBM VHDL design systemProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37960(484-490)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37960
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Design through transformation

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DAC '83: Proceedings of the 20th Design Automation Conference

June 1983

700 pages

ISBN:0818600268

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IEEE Press

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Published: 27 June 1983

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Morgan VGregory DNewton A(1991)An ECL logic synthesis systemProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127637(106-111)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127637
Suzuki SBitoh TKakimoto MTakahashi KSugimoto T(1987)TRIP: an automated technology mapping systemProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37966(523-529)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37966
Saunders L(1987)The IBM VHDL design systemProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.37960(484-490)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.37960
Wayne MBraun SOfek HO'Neill L(1985)Looking for Mr. “Turnkey”Proceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317919(405-409)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317919
Shinsha TKubo THikosaka MAkiyama KIshihara KLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)PolarisProceedings of the 21st Design Automation Conference10.5555/800033.800815(322-328)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800815
Rimkus CWayne MCheng DMagistro FRadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)Structured design verificationProceedings of the 20th Design Automation Conference10.5555/800032.800672(246-252)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800672

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A transformation from PPTL to S1S

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A transformation from PPTL to S1S

Proving Theorems by Program Transformation

A Generative Design Method Based on a Graph Transformation System

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