Energy harvesting is an attractive research area to replace batteries especially for low power co... more Energy harvesting is an attractive research area to replace batteries especially for low power consumer electronics, biomedical applications and wireless sensor networks. This paper presents a modified inductive type of DC to DC boost converter. With 120mV input, it can achieve up to 1.66V output. The values of inductors required are much lower than the previous scheme. Hence, the proposed structure can be easily realized in IC form. All investigations have been carried out using HSPICE simulations.
Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tu... more Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Due to aggressive scaling, short channel devices are leaky and more prone to process variations compared to long channel MOSFETs. Various l...
2012 2nd International Conference on Power, Control and Embedded Systems, 2012
ABSTRACT The paper presents the performance comparison of a wide bandwidth Dual-X Current Conveyo... more ABSTRACT The paper presents the performance comparison of a wide bandwidth Dual-X Current Conveyor, designed using CMOS and Hybrid approaches at 32nm technology node. A hybrid configuration is obtained by utilizing both CMOS and CNFET on the same chip. CNFETs seems to be a good prospect for extending the saturating Moore's Law because of it's higher mobility, scalability and better channel electrostatics. 3-dB current bandwidth, port-resistances along with power consumption have been chosen as the key parameters for comparison. The work in this paper shows that through properly designed hybrid configuration, an edge in performance could be obtained over Si CMOS, thus making it a good proposition for ultra wideband circuits and systems.
2012 Third International Conference on Computer and Communication Technology, 2012
ABSTRACT This paper presents a study of MTJ-based logic circuit in terms of propagation delay, po... more ABSTRACT This paper presents a study of MTJ-based logic circuit in terms of propagation delay, power dissipation, and power-delay product. The paper also analyzes impact of PVT (process, voltage, and temperature) variations on most of the design metrics of logic circuit and compares the results with those conventional CMOS logic circuit. The MTJ-based logic circuit are found to be robust compared with conventional CMOS logic circuits at the cost longer delay and higher power dissipation.
2011 International Symposium on Electronic System Design, 2011
... Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan Department of Electronics Engineering Aligarh Musl... more ... Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan Department of Electronics Engineering Aligarh Muslim University Aligarh, Uttar Pradesh, India ajmal_kafeel@hotmail.com Abstract—The active power is one of the major contributors to the total power consumption in the SRAM cell. ...
2011 International Conference on Multimedia, Signal Processing and Communication Technologies, 2011
Abstract Specific class of applications having moderate throughput and low power budget puts pres... more Abstract Specific class of applications having moderate throughput and low power budget puts pressing need on ultralow energy level operation of device instead of higher performance. Ultralow energy operation is possible only in subthreshold region and is ...
Extensive development in portable devices imposes pressing need for designing VLSI circuits with ... more Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most pro...
Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tu... more Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Therefore, this paper presents a comparative study of CMOS version and CNFET version of Operational amplifier at 32-nm technology nodes. The performance of CNFET based amplifier has been thoroughly investigated in terms of its input resistance, output resistance and AC gain. This study shows that there is considerable improvement in the above feature of amplifier using CNFET. It is founded that CNFET based amplifier have 9 times AC gain, 100 times input résistance and output resistance decrease by 9 times compared to MOSFET based amplifier at 32-nm technology node. Furthermore, comparison between two technologies for same gain bandwidth product (GBP) has also been presented.
Energy harvesting is an attractive research area to replace batteries especially for low power co... more Energy harvesting is an attractive research area to replace batteries especially for low power consumer electronics, biomedical applications and wireless sensor networks. This paper presents a modified inductive type of DC to DC boost converter. With 120mV input, it can achieve up to 1.66V output. The values of inductors required are much lower than the previous scheme. Hence, the proposed structure can be easily realized in IC form. All investigations have been carried out using HSPICE simulations.
Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tu... more Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Due to aggressive scaling, short channel devices are leaky and more prone to process variations compared to long channel MOSFETs. Various l...
2012 2nd International Conference on Power, Control and Embedded Systems, 2012
ABSTRACT The paper presents the performance comparison of a wide bandwidth Dual-X Current Conveyo... more ABSTRACT The paper presents the performance comparison of a wide bandwidth Dual-X Current Conveyor, designed using CMOS and Hybrid approaches at 32nm technology node. A hybrid configuration is obtained by utilizing both CMOS and CNFET on the same chip. CNFETs seems to be a good prospect for extending the saturating Moore's Law because of it's higher mobility, scalability and better channel electrostatics. 3-dB current bandwidth, port-resistances along with power consumption have been chosen as the key parameters for comparison. The work in this paper shows that through properly designed hybrid configuration, an edge in performance could be obtained over Si CMOS, thus making it a good proposition for ultra wideband circuits and systems.
2012 Third International Conference on Computer and Communication Technology, 2012
ABSTRACT This paper presents a study of MTJ-based logic circuit in terms of propagation delay, po... more ABSTRACT This paper presents a study of MTJ-based logic circuit in terms of propagation delay, power dissipation, and power-delay product. The paper also analyzes impact of PVT (process, voltage, and temperature) variations on most of the design metrics of logic circuit and compares the results with those conventional CMOS logic circuit. The MTJ-based logic circuit are found to be robust compared with conventional CMOS logic circuits at the cost longer delay and higher power dissipation.
2011 International Symposium on Electronic System Design, 2011
... Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan Department of Electronics Engineering Aligarh Musl... more ... Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan Department of Electronics Engineering Aligarh Muslim University Aligarh, Uttar Pradesh, India ajmal_kafeel@hotmail.com Abstract—The active power is one of the major contributors to the total power consumption in the SRAM cell. ...
2011 International Conference on Multimedia, Signal Processing and Communication Technologies, 2011
Abstract Specific class of applications having moderate throughput and low power budget puts pres... more Abstract Specific class of applications having moderate throughput and low power budget puts pressing need on ultralow energy level operation of device instead of higher performance. Ultralow energy operation is possible only in subthreshold region and is ...
Extensive development in portable devices imposes pressing need for designing VLSI circuits with ... more Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most pro...
Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tu... more Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Therefore, this paper presents a comparative study of CMOS version and CNFET version of Operational amplifier at 32-nm technology nodes. The performance of CNFET based amplifier has been thoroughly investigated in terms of its input resistance, output resistance and AC gain. This study shows that there is considerable improvement in the above feature of amplifier using CNFET. It is founded that CNFET based amplifier have 9 times AC gain, 100 times input résistance and output resistance decrease by 9 times compared to MOSFET based amplifier at 32-nm technology node. Furthermore, comparison between two technologies for same gain bandwidth product (GBP) has also been presented.
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