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ORCID9th Asian Test Symposium 2000: Taipei, Taiwan
- 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan. IEEE Computer Society 2000, ISBN 0-7695-0887-1
Keynote Address I
- Vishwani D. Agrawal, Kwang-Ting Cheng:
Testing in the Fourth Dimension. 2
Keynote Address II
- Melvin A. Breuer, Kwang-Ting Cheng:
Challenges for the Academic Test Community. 4
Industry Session I: CAD Tools on Testing
- Hsin-Po Wang, Jon Turino:
DFT and BIST techniques for the future. 6-7 - Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu:
DFT closure. 8-9 - Wu-Tung Cheng:
Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. 10-
Industry Session II: Taiwan Test Industry: Value Added Testing in the New Millennium
- Chin-Long Wey, Adam Osseiran, José Luis Huertas, Yeon-Chen Nieu:
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way. 15
- Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu:
Collaboration between Industry and Academia in Test Research. 17
Analog & Mixed Signal Test I
- Sasikumar Cherubal, Abhijit Chatterjee:
Test generation for fault isolation in analog circuits using behavioral models. 19-24 - Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault diagnosis for linear analog circuits. 25-30 - Gloria Huertas, Diego Vázquez, Eduardo J. Peralías
, Adoración Rueda, José L. Huertas:
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. 31-38 - K. Y. Ko, Mike W. T. Wong:
New built-in self-test technique based on addition/subtraction of selected node voltages. 39-
Memory Built-in Self-Test and Self-Diagnosis
- Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM. 45-50 - Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips. 51-57 - Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for SRAM cluster interconnect testing at board level. 58-65 - Sying-Jyan Wang, Chen-Jung Wei:
Efficient built-in self-test algorithm for memory. 66-
Analog & Mixed Signal Test II
- Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota:
Optimal test-set generation for parametric fault detection in switched capacitor filters. 72-77 - Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. 78-83 - Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee:
Analog circuit equivalent faults in the D.C. domain. 84-89 - Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su:
A methodology for fault model development for hierarchical linear systems. 90-95 - José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski:
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. 96-
Fault Simulation & Timing Simulation
- Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation. 102-107 - Irith Pomeranz, Sudhakar M. Reddy:
On the feasibility of fault simulation using partial circuit descriptions. 108-113 - Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy:
Fsimac: a fault simulator for asynchronous sequential circuits. 114-119 - Arabi Keshk, Yukiya Miura, Kozo Kinoshita:
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. 120-124 - Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda:
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis. 125-
Fault Analysis I
- Said Hamdioui, Ad J. van de Goor:
An experimental analysis of spot defects in SRAMs: realistic fault models and tests. 131-138 - Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs. 139-144 - Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min:
A waveform simulator based on Boolean process. 145-150 - Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. 151-
Test Generation I
- Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Compaction-based test generation using state and fault information. 159-164 - Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita:
Test sequence compaction for sequential circuits with reset states. 165-170 - Emil Gizdarski, Hideo Fujiwara:
Spirit: satisfiability problem implementation for redundancy identification and test generation. 171-178 - Shiyi Xu, Wei Cen:
Forecasting the efficiency of test generation algorithms for digital circuits. 179-
Functional Testing
- Yiorgos Makris, Jamison Collins, Alex Orailoglu:
Fast hierarchical test path construction for DFT-free controller-datapath circuits. 185-190 - Junichi Hirase, Shinichi Yoshimura:
Faster processing for microprocessor functional ATPG. 191-197 - Hiromi Hiraishi:
Verification of deadlock free property of high level robot control. 198-203 - Rajesh Kannah, C. P. Ravikumar:
Functional Testing of Microprocessors with Graded Fault Coverage. 204-
Built-in Self-Test I
- Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara:
Single-control testability of RTL data paths for BIST. 210-215 - S. L. Lin, S. Mourad, S. Krishnan:
A BIST methodology for at-speed testing of data communications transceivers. 216-221 - Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu:
High-speed generation of LFSR signatures. 222-
Software Testing & Test Synthesis
- Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara:
Strong self-testability for data paths high-level synthesis. 229-234 - Masayuki Hirayama, Jiro Okayasu, Tetsuya Yamamoto, Osamu Mizuno, Tohru Kikuno:
Generating test items for checking illegal behaviors in software testing. 235-240 - Jin-Cherng Lin, Pu-Lin Yeh:
Using genetic algorithms for test case generation in path testing. 241-
Embedded-Core Testing
- Kuen-Jong Lee, Cheng-I Huang:
A hierarchical test control architecture for core based design. 248-253 - Ruofan Xu, Michael S. Hsiao:
Embedded core testing using genetic algorithms. 254-259 - Ameet Bagwe, Rubin A. Parekhji:
Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. 260-
Memory Testing
- Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou:
etection of SRAM cell stability by lowering array supply voltage. 268-273 - Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang:
A realistic fault model for flash memories. 274-281 - Zaid Al-Ars, Ad J. van de Goor:
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. 282-289 - Wen-Jer Wu, Chuan Yi Tang:
Memory test time reduction by interconnecting test items. 290-298 - Der-Cheng Huang, Wen-Ben Jone:
An efficient parallel transparent diagnostic BIST. 299-
Test Generation II
- Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced faults: framework and computational result. 305-310 - Bin Liu, Fabrizio Lombardi, Wei-Kang Huang:
Testing programmable interconnect systems: an algorithmic approach. 311-316 - Irith Pomeranz, Sudhakar M. Reddy:
Reducing test application time for full scan circuits by the addition of transfer sequences. 317-322 - Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. 323-328 - Y. Morihiro, T. Toneda:
Formal verification of data-path circuits based on symbolic simulation. 329-
IDDQ Testing
- Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? 338-343 - Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda:
High speed IDDQ test and its testability for process variation. 344-349 - Toshiyuki Maeda, Kozo Kinoshita:
Memory reduction of IDDQ test compaction for internal and external bridging faults. 350-355 - Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita:
A high-speed IDDQ sensor implementation. 356-361 - Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi:
Cyclic greedy generation method for limited number of IDDQ tests. 362-
Built-in Self-Test II
- Wei-Lun Wang, Kuen-Jong Lee:
Accelerated test pattern generators for mixed-mode BIST environments. 368-373 - Paul Chang, Brion L. Keller, Sarala Paliwal:
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. 374-379 - Andrzej Hlawiczka, Michal Kopec:
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. 380-385 - Lijian Li, Yinghua Min:
An efficient BIST design using LFSR-ROM architecture. 386-
Testability Analysis and Design for Testability
- Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang:
Novel techniques for improving testability analysis. 392-397 - Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
A class of sequential circuits with combinational test generation complexity under single-fault assumption. 398-403 - Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. 404-
Fault Tolerance
- Abderrahim Doumar, Hideo Ito:
Testing approach within FPGA-based fault tolerant systems. 411-416 - Fabian Vargas, Alexandre M. Amory:
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis. 417-422 - Naotake Kamiura, Takashi Kodera, Nobuyuki Matsui:
Fault tolerant multistage interconnection networks with widely dispersed paths. 423-428 - Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu:
A Testable/Fault Tolerant FFT Processor Design. 429-
Fault Analysis II
- Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits. 435-440 - Eric W. MacDonald, Nur A. Touba:
Testing domino circuits in SOI technology. 441-446 - Chin-Te Kao, Sam Wu, Jwu E. Chen:
A case study of failure analysis and guardband determination for a 64M-bit DRAM. 447-
Low-Power Testing
- Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen:
Peak-power reduction for multiple-scan circuits during test application. 453-458 - Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
An adjacency-based test pattern generator for low power BIST design. 459-464 - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. 465-470
Self-Checking Circuits and Concurrent Fault Detection
- Michael J. Liebelt, Cheng-Chew Lim:
A method for determining whether asynchronous circuits are self-checking. 472-477 - Jacob Savir:
On testing safety-sensitive digital systems. 478-483 - Ismet Bayraktaroglu, Alex Orailoglu:
Accumulation-based concurrent fault detection for linear digital state variable systems. 484-
Tutorial 1
- Shi-Yu Huang, Sudhakar M. Reddy:
High Performance/Delay Testing. 490
Tutorial 2
- Tsin-Yuan Chang, Yervant Zorian:
SoC Testing and P1500 Standard. 492
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