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ORCIDIEEE Journal of Solid-State Circuits, Volume 28
Volume 28, Number 1, January 1993
- Shigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda:
BiCMOS circuit technology for high-speed DRAMs. 4-9 - Dake Liu, Christer Svensson:
Trading speed for low power by choice of supply and threshold voltages. 10-17 - Chung-Yu Wu, Kuo-Hsing Cheng, Jinn-Shyan Wang:
Analysis and design of a new race-free four-phase CMOS logic. 18-25 - Paul Vanoostende, Paul Six, Joos Vandewalle, Hugo J. De Man:
Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators. 26-39 - Joseph S. Chang, Yit Chow Tong:
A micropower-compatible time-multiplexed SC speech spectrum analyzer design. 40-48 - Anthony Rizzi:
N-delta and differential average signal processors: detailing of their signal and noise response. 49-58 - Ugur Çilingiroglu:
A charge-based neural Hamming classifier. 59-67 - Bosco Leung:
BiCMOS current cell and switch for digital-to-analog converters. 68-71 - Tung-Li Shen, James C. Daly, Jien-Chung Lo:
A 2-ns detecting time, 2- mu m CMOS built-in current sensing circuit. 72-77 - Katsuji Kimura:
A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs. 78-83 - Axel Thomsen, Martin A. Brooke:
A programmable piecewise linear large-signal CMOS amplifier. 84-89 - Morteza Vadipour:
Capacitive feedback technique for wide-band amplifiers. 90-92 - Morteza Vadipour:
A new compensation technique for resistive level shifters. 93-95
Volume 28, Number 2, February 1993
- Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Katsunari Shibata, Mitsuo Ooyama, Minoru Yamada, Takahiro Sakaguchi, Masashi Hashimoto:
A self-learning digital neural network using wafer-scale LSI. 106-114 - Haruhiko Ichino:
20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems. 115-122 - Fang Lu, Henry Samueli:
A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design. 123-132 - Minkyu Song, Yongman Lee, Wonchan Kim:
A clock feedthrough reduction circuit for switched-current systems. 133-137 - Simon Blythe, Beatrice Fraboni, Sanjay Lall, Haroon Ahmed, Ugo de Riu:
Layout reconstruction of complex silicon chips. 138-145 - Jitendra Khare, Derek B. I. Feltham, Wojciech Maly:
Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. 146-156 - S. Hadri, Bosco Leung:
Impedance boosting techniques based on BiCMOS technology. 157-161 - Daejeong Kim, Joongsik Kih, Wonchan Kim:
A new waveform-reshaping circuit: an alternative approach to Schmitt trigger. 162-164 - Jien-Chung Lo:
Novel area-time efficient static CMOS totally self-checking comparator. 165-168 - Vivek K. De, James D. Meindl:
An analytical threshold voltage and subthreshold current model for short-channel MESFETs. 169-172 - Richard X. Gu, Mohamed I. Elmasry, David J. Roulston:
A new model for bipolar transistors at high current. 173-175 - Abdel Halim Shousha, M. Aboulwafa:
A generalized tanh law MOSFET model and its applications to CMOS inverters. 176-179 - Vivek K. De, James D. Meindl:
An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs. 180-183 - Robert M. Fox:
Comments on circuit models for MOSFET thermal noise. 184-185
Volume 28, Number 3, March 1993
- Stephen W. Director, Peter Feldmann, Kannan Krishna:
Statistical integrated circuit design. 193-202 - Chris M. Kurker, John J. Paulos, Ronald S. Gyurcsik, Jye-Chyi Lu:
Hierarchical yield estimation of large analog integrated circuits. 203-209 - Iikender Agi, Paul J. Hurst, K. Wayne Current:
An image processing IC for backprojection and spatial histogramming in a pipelined array. 210-221 - Allan L. Silburt, Richard S. Phillips, G. F. Randall Gibson, Steven W. Wood, Armin G. Bluschke, James S. Fujimoto, Stephen P. Kornachuk, Benoit Nadeau-Dostie, Rajesh K. Verma, Peter M. J. Diedrich:
A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM. 222-232 - Prabir C. Maulik, L. Richard Carley, David J. Allstot:
Sizing of cell-level analog circuits using constrained optimization techniques. 233-241 - Catherine H. Gebotys:
Synthesizing embedded speed-optimized architectures. 242-252 - Jurg K. Hinderling, Tim Rueth, Ken Easton, Dawn Eagleson, Dan Kindred, Richard Kerr, Jeff Levin:
CDMA mobile station modem ASIC. 253-260 - Volker Meyer zu Bexten, Claudio Moraga, Roland Klinke, Werner Brockherde, Klaus-Gunther Hess:
ALSYN: flexible rule-based layout synthesis for analog IC's. 261-268 - Jay H. O'Neill, Bryan D. Ackland, Sailesh K. Rao, Mehdi Hatamian:
A 200 MHz CMOS broad-band switching chip. 269-275 - Robert W. Hamlin, Bud Parruck:
A SONET/SDH overhead terminator for STS-3, STS-3C, and STM-1. 276-281 - Stephen A. Jantzi, W. Martin Snelgrove, Paul F. Ferguson Jr.:
A fourth-order bandpass sigma-delta modulator. 282-291 - Michio Yotsuyanagi, Toshiyuki Etoh, Kazumi Hirata:
A 10 b 50 MHz pipelined CMOS A/D converter with S/H. 292-300 - Sudhir M. Gowda, Bing J. Sheu, Joongho Choi, Chang-Gyu Hwang, James S. Cable:
Design and characterization of analog VLSI neural network modules. 301-313 - John B. Hughes, Kenneth W. Moulding:
Switched-current signal processing for video frequencies and beyond. 314-322 - Sang-Soo Lee, Rajesh H. Zele, David J. Allstot, Guojin Liang:
CMOS continuous-time current-mode filters for high-frequency applications. 323-329 - Fang Lu, Henry Samueli:
A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS. 330-338 - Cheryl L. Stout, Joey Doernberg:
10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer. 339-343 - Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya:
A VLSI chip set for a large-scale parallel inference machine: PIM/m. 344-351 - Nobuhiro Ide, Hiroto Fukuhisa, Yoshihisa Kondo, Takeshi Yoshida, Masato Nagamatsu, Junji Mori, Itaru Yamazaki, Kiyoyi Ueno:
A 320 MFLOPS CMOS floating-point processing unit for superscalar processors. 352-361 - Livio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni:
PROXIMA: PROlog eXecutIon MAchine. 362-370 - Paul G. Y. Tsui, Bernie Pappert, Shih-Wei Sun, John R. Yeargain:
Study of BiCMOS logic gate configurations for improved low-voltage performance. 371-374 - James B. Kuo, H. J. Liao, H. P. Chen:
A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit. 375-378 - Bruce Edwards, Alan Corry, Neil Weste, Craig Greenberg:
A single-chip video ghost canceller. 379-383 - Tsutomu Wakimoto, Yukio Akazawa:
Circuits to reduce distortion in the diode-bridge track-and-hold. 384-387 - Raymond Siferd:
A GaAs four-quadrant analog multiplier circuit. 388-391 - Edison Fong, Nghiem Nguyen, Michael K. Mayes, Emmy Denton:
Design techniques for a compatible single and dual supply analog cell library. 392-396 - Barmak Mansoorian, Volkan Ozguz, Sadik Esener:
Diode-biased AC-coupled ECL-to-CMOS interface circuit. 397-399 - Alfonso Gago, R. Escaño, José A. Hidalgo-López:
Reduced implementation of D-type DET flip-flops. 400-402
Volume 28, Number 4, April 1993
- Katsuhiro Shimohigashi, Koichi Seki:
Low-voltage ULSI design. 408-413 - Yoshinobu Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, Masakazu Aoki:
Sub-1-V swing internal bus architecture for future low-power ULSIs. 414-419 - David K. Su, Marc J. Loinaz, Shoichi Masui, Bruce A. Wooley:
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. 420-430 - Craig L. Keast, Charles G. Sodini:
A CCD/CMOS-based imager with integrated focal plane signal processing. 431-437 - Hiroshi Kimura, Akira Matsuzawa, Takashi Nakamura, Shigeki Sawada:
A 10-b 300-MHz interpolated-parallel A/D converter. 438-446 - Cormac S. G. Conroy, David W. Cline, Paul R. Gray:
An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS. 447-454 - Michiel de Wit, Khen-Sang Tan, Richard K. Hester:
A low-power 12-b analog-to-digital converter with on-chip precision trimming. 455-461 - Carlos A. Laber, Paul R. Gray:
A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels. 462-470 - Gerhard Tröster, Hans-Joachim Dreßler, Hans-Joachim Golberg, Werner Schardein, Edgar Zocher, Armin Wedel, Karl Schoppe, Jürgen Arndt:
An interpolative bandpass converter on a 1.2- mu m BiCMOS analog/digital array. 471-477 - Teruo Seki, Eisaku Itoh, Chiaki Furukawa, Isamu Maeno, Tadashi Ozawa, Hiroyuki Sano, Noriyuki Suzuki:
A 6-ns 1-Mb CMOS SRAM with latched sense amplifier. 478-483 - Koichi Yokomizo, Kuniyoshi Naito:
Design techniques for high-throughput BiCMOS self-timed SRAMs. 484-489 - Natsuki Kushiyama, Shigeo Ohshima, Don Stark, Hiroyuki Noji, Kiyofumi Sakurai, Satoru Takase, Torhu Furuyama, Richard M. Barth, Andy Chan, John Dillon, James A. Gasbarro, Matthew M. Griffin, Mark Horowitz, Thomas H. Lee, Victor Lee:
A 500-megabyte/s data-rate 4.5 M DRAM. 490-498 - Seung-Moon Yoo, Ejaz Haq, Seung-Hoon Lee, Yun-Ho Choi, Soo-In Cho, Nam-Soo Kang, Daeje Chin:
Variable V/sub CC/ design techniques for battery-operated DRAMs. 499-503 - Daisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara:
Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs. 504-509 - Minoru Fujishima, Kunihiro Asada, Yasuhisa Omura, Katsutoshi Izumi:
Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates. 510-512 - Yuichi Kado, Masao Suzuki, Keiichi Koike, Yasuhisa Omura, Katsutoshi Izumi:
A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter. 513-517 - Osamu Matsuda, Shin-ichiro Hayano, Takao Takeuchi, Hideki Kitahata, Hisashi Takemura, Tsutomu Tashiro:
A Si bipolar 1.4-GHz time space switch LSI for B-ISDN. 518-522 - Tsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto:
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. 523-527
Volume 28, Number 5, May 1993
- Roberto Roncella, Roberto Saletti, Pierangelo Terreni:
70-MHz 2- mu m CMOS bit-level systolic array median filter. 530-536 - Thou-Ho Chen, Liang-Gee Chen:
Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy. 537-547 - Hsueh Y. Hsieh, Kenneth Chin, Ching-Te Chuang:
Power partition and emitter size optimization for bipolar ECL circuit. 548-552 - Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski:
Delta-sigma modulation in fractional-N frequency synthesis. 553-559 - Jorge Guilherme, F. P. Martins, João C. Vital, José E. Franca:
A CMOS analog-digital audio processor for a portable radiotelephone. 560-568 - Rajesh H. Zele, David J. Allstot, Terri S. Fiez:
Fully balanced CMOS current-mode circuits. 569-575 - Joongho Choi, Bing J. Sheu:
A high-precision VLSI winner-take-all circuit for self-organizing neural networks. 576-584 - Yusuf Leblebici, Sung-Mo Kang:
Modeling and simulation of hot-carrier-induced device degradation in MOS circuits. 585-595 - Vivek K. De, James D. Meindl:
Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction. 596-604 - Germano Nicollini, Yves Mazoyer, Carlo Crippa, Sergio Pernici, Pierangelo Confalonieri:
A CMOS fully integrated antilarsen system for digital telephones. 605-609 - Wei Li:
A transistor-only low-pass filter with adjustable bias and small phase shift at high frequencies. 610-612 - B. S. Wu, Ching-Te Chuang, K. Chin:
Non-quasi-static effects in advanced high-speed bipolar circuits. 613-617
Volume 28, Number 6, June 1993
- Gitty N. Nasserbakht, James W. Adkisson, Bruce A. Wooley, James S. Harris Jr., Theodore I. Kamins:
A monolithic GaAs-on-Si receiver front end for optical interconnect systems. 622-630 - Michael Cooperman, Phil Andrade:
CMOS gigabit-per-second switching. 631-639 - Guangming Yin, Frederic Stubbe, Willy Sansen:
A 16-b 320-kHz CMOS A/D converter using two-stage third-order Sigma Delta noise shaping. 640-647 - Mohammad Sarhang-Nejad, Gabor C. Temes:
A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements. 648-660 - J. Francisco Duque-Carrillo, José M. Valverde, Raquel Pérez-Aloe:
Constant-G/sub m/ rail-to-rail common-mode range input stage with minimum CMRR degradation. 661-666 - Made Gunawan, Gerard C. M. Meijer, Jeroen Fonderie, Johan H. Huijsing:
A curvature-corrected low-voltage bandgap reference. 667-670 - Ho-Jun Song, Choong-Ki Kim:
A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET's. 671-677 - Robert M. Fox, Sang-Gug Lee, David T. Zweidinger:
The effects of BJT self-heating on circuit behavior. 678-685 - Massimo Lanzoni, Michele Favalli, M. Ambanelli, Piero Olivo, Bruno Riccò:
An experimental study of testing techniques for bridging faults in CMOS ICs. 686-690 - Paul J. Hurst, Roger A. Levinson, David J. Block:
A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain. 691-696 - Sen Jung Wei, Hung Chang Lin, Robert C. Potter, Dave Shupe:
A self-latching A/D converter using resonant tunneling diodes. 697-700 - Luca Selmi, Bruno Riccò:
Design of an X-band transformer-coupled amplifier with improved stability and layout. 701-703 - Mark G. Johnson:
An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier. 704-705
Volume 28, Number 7, July 1993
- Bruno Stefanelli, Andreas Kaiser:
A 2- mu m CMOS fifth-order low-pass continuous-time filter for video-frequency applications. 713-718 - José L. Huertas, Adoración Rueda, Diego Vázquez:
Testable switched-capacitor filters. 719-724 - André Abrial, Jacky Bouvier, Jean-Michel Fournier, Patrice Senn:
A low-power 8-b 1 3.5-MHz video CMOS ADC for visiophony ISDN applications. 725-729 - Toshiyuki Okamoto, Yuichi Maruyama, Akira Yukawa:
A stable high-order delta-sigma modulator with an FIR spectrum distributor. 730-735 - Olivier J. A. P. Nys, Evert Dijkstra:
On configurable oversampled A/D converters. 736-742 - Bernard J. van den Dool, Johan H. Huijsing:
Indirect current feedback instrumentation amplifier with a common-mode input range that includes the negative roll. 743-749 - Gert van der Horn, Johan H. Huijsing:
Extension of the common-mode range of bipolar input stages beyond the supply rails of operational amplifiers and comparators. 750-757 - Sergio Pernici, Germano Nicollini, Rinaldo Castello:
A CMOS low-distortion fully differential power amplifier with double nested Miller compensation. 758-763 - Max A. Hilhorst, Jos Balendonck, Frans W. H. Kampers:
A broad-bandwidth mixed analog/digital integrated circuit for the measurement of complex impedance. 764-769 - Rinaldo Castello, Luciano Tomasini:
A BiCMOS speech circuit with only two external components. 770-777 - Carlo Guardiani, Primo Scandolara, Jacques Benkoski, Germano Nicollini:
Yield optimization of analog ICs using two-step analytic modeling methods. 778-783 - Gijs van Steenwijk, Klaas Hoen, Hans Wallinga:
A nonvolatile analog programmable voltage source using the VIPMOS EEPROM structure. 784-788 - Thierry M. Bernard, Bertrand Y. Zavidovique, Francis J. Devos:
A programmable artificial retina. 789-798 - J. Mikko Hakkarainen, Hae-Seung Lee:
A 40*40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system. 799-807 - Harufusa Kondoh, Hiromi Notani, Hideaki Yamanaka, Keiichi Higashitani, Hirotaka Saito, Isamu Hayashi, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima, Masao Nakaya:
A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. 808-815 - Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki:
A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. 816-823 - Rainer H. Derksen, Horst Wernz:
Silicon bipolar laser driving IC for 5 Gb/s and 45-mA modulation current and its application in a demonstrator system. 824-828 - Zhi-Gong Wang, Manfred Berroth, Ulrich Nowotny, Manfred Ludwig, Peter Hofmann, Axel Hülsmann, Klaus Köhler, Brian Raynor, Joachim Schneider:
Integrated laser-diode voltage driver for 20-Gb/s optical systems using 0.3- mu m gate length quantum-well HEMT's. 829-834 - Anna M. Durham, William Redman-White:
Integrated continuous-time balanced filters for 16-b DSP interfaces. 835-839 - Ivan Riis Nielsen:
A novel SFG structure for C-T high-pass filters. 840-844 - Giuseppe Caiulo, Franco Maloberti, Giuseppe Palmisano, S. Portaluri:
Video CMOS power buffer with extended linearity. 845-848 - Thomas Kaulberg:
A CMOS current-mode operational amplifier. 849-852 - A. Rothermel, Francis Dell'ova:
Analog phase measuring circuit for digital CMOS ICs. 853-856 - Thorsten Kettner, Christian Heite, Klaus Schumacher:
Analog CMOS realization of fuzzy logic membership functions. 857-861 - L. A. Dick Van Den Broeke, A. J. Nieuwkerk:
Wide-band integrated optical receiver with improved dynamic range using a current switch at the input. 862-864 - Jürgen Oehm, Klaus Schumacher:
Quality assurance and upgrade of analog characteristics by fast mismatch analysis option in network analysis environment. 865-871 - Philippe Duchene, Michel J. Declercq, B. Goffart, M. Novak:
Analog circuit implementation on CMOS semi-custom arrays. 872-874
Volume 28, Number 8, August 1993
- Fang Lu, Henry Samueli, Jiren Yuan, Christer Svensson:
A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator. 878-886 - Timo Rahkonen, Juha T. Kostamovaara:
The use of stabilized CMOS delay lines for the digitization of short time intervals. 887-894 - Chung-Yu Wu, Hong-Yi Huang:
Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic. 895-906 - Christian R. Schneider, Howard C. Card:
Analog CMOS deterministic Boltzmann circuits. 907-914 - Germano Nicollini, Carlo Guardiani:
A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique. 915-921 - Richard E. Colbeth, Ross A. LaRue:
A CCD frequency prescaler for broadband applications. 922-930
Volume 28, Number 9, September 1993
- Yuu Watanabe, Yasuhiro Nakasha, Yuji Kato, Kohichiro Odani, Masayuki Abe:
A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO. 935-940 - Tai-ichi Otsuji:
A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI. 941-947 - Mark Royals, Tassos Markas, Nick Kanopoulos, John H. Reif, James A. Storer:
On the design and implementation of a lossless data compression and decompression chip. 948-953 - Jan Peter Moree, Gert Groenewold, L. A. Dick Van Den Broeke:
A bipolar integrated continuous-time filter with optimized dynamic range. 954-961 - Rui Paulo Martins, José E. Franca, Franco Maloberti:
An optimum CMOS switched-capacitor antialiasing decimating filter. 962-970 - Bruno Stefanelli, Jean-Paul Bardyn, Andreas Kaiser, Daniel Billet:
A very low-noise CMOS preamplifier for capacitive sensors. 971-978 - Larry T. Wurtz:
An efficient scaling procedure for domain CMOS logic. 979-982
Volume 28, Number 10, October 1993
- Huei Wang, Thuy-Nhung Ton, Kin L. Tan, Diane C. Garske, Gee Samuel Dow, John B. Berenz, Marian W. Pospieszalski, Shing-Kuo Pan:
110-120-GHz monolithic low-noise amplifiers. 988-993 - Kazuya Yamamoto, Kosei Maemura, Naoto Andoh, Yasuo Mitsui:
A 1.9-GHz-band GaAs direct-quadrature modulator IC with a phase shifter. 994-1000 - Howard Fudem, Sanjay Moghe, Greg Dietz:
A highly integrated wideband millimeter-wave MMIC converter using 0.25- mu m P-HEMT technology. 1001-1004 - Thomas Arell, Thongchai Hongsmatip:
A unique MMIC broadband power amplifier approach. 1005-1010 - Kevin W. Kobayashi, Donald K. Umemoto, James R. Velebir Jr., Aaron K. Oki, Dwight C. Streit:
Integrated complementary HBT microwave push-pull and Darlington amplifiers with p-n-p active loads. 1011-1017 - I. Ross MacTaggart, Mark Bendett, Stewart S. Taylor:
A complete 400-Mb/s burst-mode data OEIC receiver. 1018-1022 - Stewart S. Taylor:
A high-performance GaAs pin electronics circuit for automatic test equipment. 1023-1029 - Richard B. Brown, Michael Upton, Ajay Chandna, Thomas R. Huff, Trevor N. Mudge, Richard E. Oettel:
Gallium-arsenide process evaluation based on a RISC microprocessor example. 1030-1037 - Peter Stuhr Lassen, Stephen I. Long, Kevin R. Nary:
Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic. 1038-1045 - Makoto Shikata, Koutarou Tanaka, Hiromi T. Yamada, Hiroki I. Fujishiro, Seiji Nishi, Chouho Yamagishi, Masahiro Akiyama:
A 20-Gb/s flip-flop circuit using direct-coupled FET logic. 1046-1051 - Albert C. van der Woerd, Wouter A. Serdijn:
Low-voltage low-power controllable preamplifier for electret microphones. 1052-1055 - Eric Bruls, Manoj Sachdev, Keith Baker:
Comments on 'Totally self-checking CMOS circuit design for breaks and stuck-on faults'. 1056-1057
Volume 28, Number 11, November 1993
- Michio Sasaki, Hisanori Ihara, Yoshiyuki Matsunaga:
A 2/3-in 400k-pixel sticking-free stack-CCD image sensor. 1066-1070 - Yuichi Saito, Yukihiko Shimazu, Tom Shimizu, Kenji Shirai, Isao Fujioka, Yoshitetsu Nishiwaki, Junichi Hinata, Yoshiki Shimotsuma, Masayoshi Sakao:
A 1.71-million transistor CMOS CPU chip with a testable cache architecture. 1071-1077 - Raymond A. Heald, John Holst:
A 6-ns cycle 256-kb cache memory and memory management unit. 1078-1083 - Hiroyuki Yamauchi, Toshikazu Suzuki, Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita, Michihiro Inoue:
A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. 1084-1091 - Tadahiko Sugibayashi, Toshio Takeshima, Isao Naritake, Tatsuya Matano, Hiroshi Takada, Yoshiharu Aimoto, Koichiro Furuta, Mamoru Fujita, Takanori Saeki, Hiroshi Sugawara, Tatsunori Murotani, Naoki Kasai, Kentaro Shibahara, Ken Nakajima, Hiromitsu Hada, Takehiko Hamada, Naoaki Aizaki, Takemitsu Kunio, Eiichiro Kakehashi, Katsuhiro Masumori, Takaho Tanigawa:
A 30-ns 256-Mb DRAM with a multidivided array structure. 1092-1098 - Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka:
An experimental DRAM with a NAND-structured cell. 1099-1104 - Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida:
256-Mb DRAM circuit technologies for file applications. 1105-1113 - Motomu Ukita, Shuji Murakami, Tadato Yamagata, Hirotada Kuriyama, Yasumasa Nishimura, Kenji Anami:
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's. 1114-1118 - Katsunori Seno, Kurt Knorpp, Lee-Lean Shu, Naoki Teshima, Hiroki Kihara, Hiroshi Sato, Fumio Miyaji, Minoru Takeda, Masayoshi Sasaki, Yoichi Tomo, Patrick T. Chuang, Kazuyoshi Kobayashi:
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier. 1119-1124 - Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki:
A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell. 1125-1130 - Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh:
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's. 1131-1135 - Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki:
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). 1136-1144 - Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. 1145-1151 - Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey W. Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, J. Leon Yang, William R. Hamburgen, John S. Fitch, Russell Kao:
A 300-MHz 115-W 32-b bipolar ECL microprocessor. 1152-1166 - Andreas Thiede, Manfred Berroth, Ulrich Nowotny, Jorg Seibel, Roland Bosch, Klaus Köhler, Brian Raynor, Joachim Schneider:
An 18-34-GHz dynamic frequency divider based on 0.2- mu m AlGaAs/GaAs/AlGaAs quantum-well transistors. 1167-1169
Volume 28, Number 12, December 1993
- Kazuya Sone, Yoshio Nishida, Naotoshi Nakadai:
A 10-b 100-Msample/s pipelined subranging BiCMOS ADC. 1180-1186 - William T. Colleran, Asad A. Abidi:
A 10-b, 75-MHz two-stage pipelined bipolar A/D converter. 1187-1199 - Keiichi Kusumoto, Akira Matsuzawa, Kenji Murata:
A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC. 1200-1206 - Andrew N. Karanicolas, Hae-Seung Lee, Kantilal L. Barcrania:
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. 1207-1215 - John W. Fattaruso, Sami Kiriaki, Michiel de Wit, Greg Warwar:
Self-calibration techniques for a second-order multibit sigma-delta modulator. 1216-1223 - David K. Su, Bruce A. Wooley:
A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter. 1224-1233 - Scott D. Willingham, Kenneth W. Martin, Ashwin Ganesan:
A BiCMOS low-distortion 8-MHz low-pass filter. 1234-1245 - Mikio Koyama, Tadashi Arai, Hiroshi Tanimoto, Yoshihiro Yoshida:
A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a 1-V/sub p-p/ range. 1246-1253 - Un-Ku Moon, Bang-Sup Song:
Design of a low-distortion 22-kHz fifth-order Bessel filter. 1254-1264 - Paul C. Yu, Hae-Seung Lee:
A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement. 1265-1272 - John G. Maneatis, Mark A. Horowitz:
Precise delay generation using coupled oscillators. 1273-1282 - Sang-Soo Lee, David J. Allstot:
Electrothermal simulation of integrated circuits. 1283-1293 - Thomas W. Matthews, Richard R. Spencer:
An integrated analog CMOS Viterbi detector for digital magnetic recording. 1294-1302 - Matthias Bussmann, Ulrich Langmann, Wiliam J. Hillery, Wiliam W. Brown:
A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s. 1303-1309 - Mehmet Soyuer:
A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology. 1310-1313 - Timothy H. Hu, Paul R. Gray:
A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS. 1314-1320 - Toshiaki Inoue, Junichi Goto, Masakazu Yamashina, Kazumasa Suzuki, Masahiro Nomura, Youichi Koseki, Tohru Kimura, Takao Atsumo, Masato Motomura, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, Masahide Takada:
A 300-MHz 16-b BiCMOS video signal processor. 1321-1330 - Ken A. Nishimura, Paul R. Gray:
A monolithic analog video comb filter in 1.2- mu m CMOS. 1331-1339 - Angel Bóveda, José I. Alonso:
A 0.7-3 GHz GaAs QPSK/QAM direct modulator. 1340-1349 - Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong:
Class-AB large-swing CMOS buffer amplifier with controlled bias current. 1350-1353 - Marco Winzker, Klaus Grüger, Winfried Gehrke, Peter Pirsch:
VLSI chip set for 2D HDTV subband filtering with on-chip line memories. 1354-1361 - Toru Shiomi, Tomohisa Wada, Shigeki Ohbayashi, Atsushi Ohba, Hiroki Honda, Yoshiyuki Ishigaki, Shiro Hine, Kenji Anami, Kimio Suzuki, Tadashi Sumi:
A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. 1362-1369 - Michael Dolle:
A dynamic line-termination circuit for multireceiver nets. 1370-1373 - Ching-Te Chuang, K. Chin, Pong-Fei Lu, H. J. Shin:
High-speed low-power Darlington ECL circuit. 1374-1376 - Jeffrey Gray, Andrew Naylor, Arthur Abnous, Nader Bagherzadeh:
VIPER: a VLIW integer microprocessor. 1377-1382 - Ramesh Senthinathan, John L. Prince:
Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise. 1383-1388 - Samir S. Rofail, Mohamed I. Elmasry:
Analysis of latchup and parasitic effects in merged BiCMOS structures. 1389-1394 - Yannis P. Tsividis:
Comment on "A nonlinear CMOS analog cell for VLSI signal and information processing". 1395
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