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ORCIDJames D. Meindl
Person information
- affiliation: Georgia Institute of Technology, Atlanta GA, USA
- award (2006): IEEE Medal of Honor
- award (1990): IEEE James H. Mulligan, Jr. Education Medal
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2010 – 2019
- 2010
[c35]James D. Meindl, Azad Naeemi
, Muhannad S. Bakir, R. Murali:
Nanoelectronics in retrospect, prospect and principle. ISSCC 2010: 31-35
2000 – 2009
- 2008
- [j25]Kaveh Shakeri, James D. Meindl:
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 745-754 (2008) - [c34]Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl:
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC 2008: 663-670 - [c33]Azad Naeemi, James D. Meindl:
Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD 2008: 400-405 - 2007
- [c32]Muhannad S. Bakir, Bing Dang, James D. Meindl:
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. CICC 2007: 421-428 - [c31]Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl:
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC 2007: 841-844 - [c30]Azad Naeemi, Reza Sarvari, James D. Meindl:
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC 2007: 568-573 - [c29]Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl:
IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD 2007: 560-567 - [c28]Azad Naeemi, James D. Meindl:
Carbon nanotube interconnects. ISPD 2007: 77-84 - 2006
- [c27]Hiren D. Thacker, James D. Meindl:
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. ITC 2006: 1-7 - 2004
- [j24]James W. Joyner, Payman Zarkesh-Ha, James D. Meindl:
Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 367-372 (2004) - [c26]Kaveh Shakeri, James D. Meindl:
Relative inductance extraction method. CICC 2004: 481-484 - [c25]Kaveh Shakeri, Muhannad S. Bakir, James D. Meindl:
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. SoCC 2004: 78-81 - 2003
- [j23]James D. Meindl:
Beyond Moore's Law: the interconnect era. Comput. Sci. Eng. 5(1): 20-24 (2003) - [j22]James D. Meindl:
Interconnect Opportunities for Gigascale Integration. IEEE Micro 23(3): 28-35 (2003) - [j21]Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills:
Modeling technology impact on cluster microprocessor performance. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 909-920 (2003) - 2002
- [j20]James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl:
Interconnect opportunities for gigascale integration. IBM J. Res. Dev. 46(2-3): 245-264 (2002) - [j19]Keith A. Bowman, Steven G. Duvall, James D. Meindl:
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37(2): 183-190 (2002) - [j18]A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl:
Electrical and optical clock distribution networks for gigascale microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 582-594 (2002) - [c24]Muhannad S. Bakir, Hollie A. Reed, Anthony V. Mulé, Paul A. Kohl, Kevin P. Martin, James D. Meindl:
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. CICC 2002: 491-494 - [c23]Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl:
A physical model for the transient response of capacitively loaded distributed rlc interconnects. DAC 2002: 763-766 - [c22]Kaveh Shakeri, James D. Meindl:
A compact delay model for series-connected MOSFETs. ACM Great Lakes Symposium on VLSI 2002: 37-40 - [c21]R. Murali, Lihui Wang, Blanca Austin, James D. Meindl:
Low-power circuit advantages of the scaled accumulation FET. ISCAS (5) 2002: 201-204 - [c20]Kaveh Shakeri, James D. Meindl:
Temperature Variable Supply Voltage for Power Reduction. ISVLSI 2002: 71-74 - 2001
- [j17]Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl:
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits 36(4): 658-665 (2001) - [j16]James D. Meindl:
Special issue on limits of semiconductor technology. Proc. IEEE 89(3): 223-226 (2001) - [j15]Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl:
Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE 89(3): 305-324 (2001) - [j14]Lucian Codrescu, D. Scott Wills, James D. Meindl:
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Trans. Computers 50(1): 67-82 (2001) - [j13]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 9(6): 899-912 (2001) - [j12]James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 922-928 (2001) - [c19]Keith A. Bowman, James D. Meindl:
Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC 2001: 229-232 - [c18]Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl:
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. ICCD 2001: 214-220 - [c17]Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD 2001: 400-405 - 2000
- [j11]James D. Meindl, Jeffrey A. Davis:
The fundamental limit on binary switching energy for terascale integration (TSI). IEEE J. Solid State Circuits 35(10): 1515-1516 (2000) - [j10]Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 235-251 (2000) - [j9]Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 649-659 (2000) - [j8]Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl:
Heterogeneous architecture models for interconnect-motivated system design. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 660-670 (2000) - [j7]Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl:
A compact physical via blockage model. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 689-692 (2000) - [c16]Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl:
CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI 2000: 7-12 - [c15]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED 2000: 167-172 - [c14]Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
Prediction of interconnect fan-out distribution using Rent's rule. SLIP 2000: 107-112 - [c13]James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP 2000: 123-127 - [c12]Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl:
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP 2000: 147-148
1990 – 1999
- 1999
- [j6]Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl:
A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits 34(10): 1410-1414 (1999) - [c11]James D. Meindl:
XXI Century Gigascale Integration (GSI) : The Interconnect Problem. ARVLSI 1999: 88- - [c10]Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl:
Exploring Microprocessor Architectures for Gigascale Integration. ARVLSI 1999: 242-255 - [c9]Payman Zarkesh-Ha, Tony Mule, James D. Meindl:
Characterization and modeling of clock skew with process variations. CICC 1999: 441-444 - 1998
- [c8]Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. CICC 1998: 93-96 - [c7]Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl:
Minimum supply voltage for bulk Si CMOS GSI. ISLPED 1998: 100-102 - 1997
- [j5]Xinghai Tang, Vivek De, James D. Meindl:
Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 369-376 (1997) - [c6]James D. Meindl:
A history of low power electronics: how it began and where it's headed. ISLPED 1997: 149-151 - 1996
- [c5]Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl:
Circuit techniques for low-power CMOS GSI. ISLPED 1996: 193-196 - [c4]Xinghai Tang, Vivek De, James D. Meindl:
Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED 1996: 233-236 - [c3]Vivek De, James D. Meindl:
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED 1996: 371-375 - 1995
- [j4]James D. Meindl:
Low power microelectronics: retrospect and prospect. Proc. IEEE 83(4): 619-635 (1995) - 1994
- [j3]Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl:
Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE J. Solid State Circuits 29(2): 122-125 (1994) - 1991
- [c2]James D. Meindl:
Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. ICCD 1991: 438 - [c1]James D. Meindl:
Gigascale integration (GSI) technology. SC 1991: 534-538
1980 – 1989
- 1988
- [j2]Roy E. Scheuerlein, James D. Meindl:
Offset word-line architecture for scaling DRAMs to the gigabit level. IEEE J. Solid State Circuits 23(1): 41-47 (1988) - 1986
- [j1]Kenneth A. Pickar, James D. Meindl:
Scanning the issue. Proc. IEEE 74(12): 1603-1604 (1986)
Coauthor Index
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