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2020 – today
- 2020
[j50]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey
, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55(3): 706-718 (2020)
2010 – 2019
- 2019
- [j49]Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez:
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 347-351 (2019) - [j48]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2440-2453 (2019) - [c64]Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. CICC 2019: 1-4 - [c63]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC 2019: 1-4 - 2018
- [j47]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53(3): 799-813 (2018) - [j46]James J. Sluss, Bonnie H. Ferri, Terri S. Fiez, Joseph L. A. Hughes, Rob Reilly, Ali Mehrizi-Sani, Jeffrey E. Froyd, Justin M. Foley, Shanna Daly, Catherine Lenaway, Jamie Phillips, Yu-Tzu Lin, Cheng-Chih Wu, Ting-Yun Hou, Yu-Chih Lin, Fang-Ying Yang, Chia-Hu Chang, Hitoshi Sasaki, Takako Akakura, Gabriel Díaz, Ramon Carrasco, Beth Rieken, Mark Schar, Sheri Sheppard, Stephanie Cutler, Thomas A. Litzinger, Sarah E. Zappe, Michael Alley, Edwin C. Jones:
2017 IEEE Education Society Awards, 2017 Frontiers in Education Conference Awards, and Selected IEEE Awards. IEEE Trans. Educ. 61(1): 74-83 (2018) - [c62]Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez:
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS 2018: 145-148 - 2017
- [c61]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC 2017: 1-4 - [c60]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez:
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS 2017: 1-4 - 2016
- [j45]Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez:
Fast start-up analysis of resonator based oscillators using a power generation method. IET Circuits Devices Syst. 10(5): 357-364 (2016) - [c59]Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez:
JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. WF-IoT 2016: 48-53 - 2015
- [j44]Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. IEEE J. Solid State Circuits 50(1): 291-302 (2015) - [j43]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram:
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50(8): 1833-1847 (2015) - 2014
- [c58]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC 2014: 1-4 - [c57]Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator. ISSCC 2014: 226-227 - [c56]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. VLSIC 2014: 1-2 - [c55]Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li:
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. VTS 2014: 1 - 2013
- [j42]Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez:
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits 48(2): 487-501 (2013) - [j41]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(5): 1250-1263 (2013) - 2012
- [j40]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1604-1613 (2012) - [j39]Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez:
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1614-1625 (2012) - [j38]Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 344-356 (2012) - [c54]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. VLSIC 2012: 40-41 - [c53]Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez:
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design 2012: 20-21 - 2011
- [j37]Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram:
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. IEEE J. Solid State Circuits 46(4): 938-949 (2011) - [j36]Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram:
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. IEEE J. Solid State Circuits 46(8): 1782-1795 (2011) - [j35]Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez:
A Multiple-Input Boost Converter for Low-Power Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 827-831 (2011) - [c52]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC 2011: 1-4 - [c51]Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez:
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC 2011: 1-4 - 2010
- [j34]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
An Ultralow-Power Receiver for Wireless Sensor Networks. IEEE J. Solid State Circuits 45(9): 1759-1769 (2010) - [c50]Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez:
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. CICC 2010: 1-4 - [c49]Ramin Zanbaghi, Terri S. Fiez, Gabor C. Temes:
A new zero-optimization scheme for noise-coupled ΔΣ ADCs. ISCAS 2010: 2163-2166
2000 – 2009
- 2009
- [j33]Thomas William Brown, Mikko Hakkarainen, Terri S. Fiez:
Frequency-Dependent Sampling Linearity. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(4): 740-753 (2009) - [c48]Ramin Zanbaghi, Terri S. Fiez:
A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators. ISCAS 2009: 3114-3117 - [c47]Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. ISQED 2009: 112-115 - 2008
- [j32]Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. IEEE J. Solid State Circuits 43(5): 1287-1302 (2008) - [j31]Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1595-1606 (2008) - [c46]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. CICC 2008: 591-594 - [c45]Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez:
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. CICC 2008: 595-598 - 2007
- [j30]Zhimin Li, Terri S. Fiez:
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth. IEEE J. Solid State Circuits 42(9): 1873-1883 (2007) - [c44]Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. CICC 2007: 845-848 - [c43]Brett Peterson, Kartikeya Mayaram, Terri S. Fiez:
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. CICC 2007: 853-856 - [c42]Donald Heer, Carlos Jensen, Terri S. Fiez:
Finding a Way: What can Computer Science Education Do? FECS 2007: 54-59 - [c41]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. ISCAS 2007: 1345-1348 - [c40]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
A Low Power BFSK Super-Regenerative Transceiver. ISCAS 2007: 3099-3102 - 2006
- [j29]Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. Solid State Circuits 41(3): 574-587 (2006) - [j28]Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric micro-power generation interface circuits. IEEE J. Solid State Circuits 41(6): 1411-1420 (2006) - [j27]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 932-938 (2006) - [j26]Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez:
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2578-2587 (2006) - [c39]Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. CICC 2006: 105-108 - [c38]Thomas William Brown, Terri S. Fiez, Mikko Hakkarainen:
Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. CICC 2006: 237-240 - [c37]Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. CICC 2006: 293-296 - [c36]Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram:
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. CICC 2006: 729-732 - 2005
- [j25]Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez:
Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits 40(2): 382-391 (2005) - [j24]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
On the numerical stability of Green's function for substrate coupling in integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 653-658 (2005) - [j23]Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez:
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 330-338 (2005) - [j22]Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 843-851 (2005) - [c35]Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
A green function-based parasitic extraction method for inhomogeneous substrate layers. DAC 2005: 141-146 - 2004
- [j21]Ruoxin Jiang, Terri S. Fiez:
A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. IEEE J. Solid State Circuits 39(1): 63-74 (2004) - [j20]Aria Eshraghi, Terri S. Fiez:
A comparative analysis of parallel delta-sigma ADC architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(3): 450-458 (2004) - [j19]Steven K. Dunlap, Terri S. Fiez:
A noise-shaped switching power supply using a delta-sigma modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(6): 1051-1061 (2004) - [j18]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(6): 1223-1233 (2004) - [j17]Ravindranath Naiknaware, Terri S. Fiez:
Process-insensitive low-power design of switched-capacitor integrators. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(10): 1940-1952 (2004) - [c34]Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. CICC 2004: 367-370 - [c33]Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram:
A predictive methodology for accurate substrate parasitic extraction. ISCAS (5) 2004: 149-152 - [c32]Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram:
A physical and analytical model for substrate noise coupling analysis. ISCAS (5) 2004: 157-160 - [c31]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An improved Z-parameter macro model for substrate noise coupling. ISCAS (5) 2004: 161-164 - [c30]Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram:
An accurate and efficient estimation of switching noise in synchronous digital circuits. ISCAS (2) 2004: 485-488 - [c29]Sachin Ranganathan, Terri S. Fiez:
A variable gain high linearity low power baseband filter for WLAN. ISCAS (1) 2004: 845-848 - [c28]Madhu Chennam, Terri S. Fiez:
A 0.35µm current-mode T/H with -81dB THD. ISCAS (1) 2004: 1112-1115 - [c27]Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram:
Silencer!: a tool for substrate noise coupling analysis. SoCC 2004: 105-108 - 2003
- [j16]Aria Eshraghi, Terri S. Fiez:
A time-interleaved parallel /ΔΣ A/D converter. IEEE Trans. Circuits Syst. II Express Briefs 50(3): 118-129 (2003) - [j15]Roger L. Traylor, Donald Heer, Terri S. Fiez:
Using an integrated platform for learning™ to reinvent engineering education. IEEE Trans. Educ. 46(4): 409-419 (2003) - [j14]Donald Heer, Roger L. Traylor, Tom Thompson, Terri S. Fiez:
Enhancing the freshman and sophomore ECE student experience using a platform for learning™. IEEE Trans. Educ. 46(4): 434-443 (2003) - [c26]Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez:
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC 2003: 361-364 - [c25]Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric power generation interface circuits. CICC 2003: 489-492 - [c24]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Coupled Simulation of Circuit and Piezoelectric Laminates. ISQED 2003: 369-372 - 2002
- [j13]Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A CMOS transconductor with 80-dB SFDR up to 10 MHz. IEEE J. Solid State Circuits 37(3): 365-370 (2002) - [c23]Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. CICC 2002: 497-500 - [c22]Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
The effect of supply and substrate noise on jitter in ring oscillators. CICC 2002: 505-508 - [c21]Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez:
An efficient modeling approach for substrate noise coupling analysis. ISCAS (5) 2002: 237-240 - [c20]Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram:
Analysis of jitter in ring oscillators due to deterministic noise. ISCAS (4) 2002: 393-396 - [c19]Zhimin Li, Terri S. Fiez:
Dynamic element matching in low oversampling delta sigma ADCs. ISCAS (4) 2002: 683-686 - [c18]R. Batten, Terri S. Fiez:
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer. ISCAS (3) 2002: 715-718 - 2001
- [c17]Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz. CICC 2001: 459-462 - 2000
- [j12]Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for design of mixed-signal IC's. IEEE J. Solid State Circuits 35(6): 895-904 (2000) - [j11]Russell E. Radke, Aria Eshraghi, Terri S. Fiez:
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging. IEEE J. Solid State Circuits 35(8): 1074-1084 (2000) - [c16]Ravindranath Naiknaware, Terri S. Fiez:
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. CICC 2000: 5-8
1990 – 1999
- 1999
- [j10]Ravindranath Naiknaware, Terri S. Fiez:
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. IEEE J. Solid State Circuits 34(3): 304-303 (1999) - [j9]Ravindranath Naiknaware, Terri S. Fiez:
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. IEEE J. Solid State Circuits 34(3): 304-317 (1999) - [c15]Russell E. Radke, Aria Eshraghi, Terri S. Fiez:
A spurious-free delta-sigma DAC using rotated data weighted averaging. CICC 1999: 125-128 - [c14]Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for mixed-signal ICs. ICCAD 1999: 128-131 - [c13]Ravindranath Naiknaware, Terri S. Fiez:
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ISCAS (2) 1999: 33-36 - [c12]Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. ISCAS (6) 1999: 218-221 - [c11]Ravindranath Naiknaware, Terri S. Fiez:
Switched-capacitor integrator design optimizing for power and process variations. ISCAS (2) 1999: 278-281 - 1998
- [j8]Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez:
A Nyquist-rate delta-sigma A/D converter. IEEE J. Solid State Circuits 33(1): 45-52 (1998) - [c10]Ravindranath Naiknaware, Terri S. Fiez:
Schematic driven module generation for analog circuits with performance optimization and matching considerations. CICC 1998: 481-484 - [c9]Ravindranath Naiknaware, Terri S. Fiez:
CMOS analog circuit stack generation with matching constraints. ICCAD 1998: 371-375 - 1997
- [c8]Detlev Schmitt, Terri S. Fiez:
A low voltage CMOS current source. ISLPED 1997: 110-113 - 1996
- [j7]Rex T. Baird, Terri S. Fiez:
A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC. IEEE J. Solid State Circuits 31(3): 312-320 (1996) - 1995
- [c7]Rex T. Baird, Terri S. Fiez:
Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. ISCAS 1995: 13-16 - [c6]Gregory M. Cooley, Terri S. Fiez, Bryan Buchanan:
PWM and PCM Techniques for Control of Digitally Programmable Switching Power Supplies. ISCAS 1995: 1114-1117 - 1994
- [j6]Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer:
Design of a new squaring function for the Viterbi algorithm. IEEE J. Solid State Circuits 29(9): 1102-1107 (1994) - [j5]Marius Goldenberg, Russell Croman, Terri S. Fiez:
Accurate SI filters using RGC integrators. IEEE J. Solid State Circuits 29(11): 1388-1395 (1994) - [c5]Farbod Aram, Aria Eshraghi, Terri S. Fiez:
Compact and Accurate MOST Model for Analog Circuit Hand Calculations. ISCAS 1994: 213-216 - [c4]Aria Eshraghi, Terri S. Fiez, Thomas R. Fischer:
Asynchronus Implementation for the Add Compare Select Processor for Communication Systems. ISCAS 1994: 253-256 - [c3]Ligang Zhang, Terry L. Sculley, Terri S. Fiez:
A 12 Bit, 2V Current-Mode Pipelined A/D Converter Nonlinearity. ISCAS 1994: 369-372 - 1993
- [j4]Rajesh H. Zele, David J. Allstot, Terri S. Fiez:
Fully balanced CMOS current-mode circuits. IEEE J. Solid State Circuits 28(5): 569-575 (1993) - [c2]Rex T. Baird, Terri S. Fiez:
Stability Analysis of High-order Modulators for Delta-Sigma ADCs. ISCAS 1993: 1361-1364 - [c1]Edmund M. Schneider, Terri S. Fiez:
Simulation of Switched-Current Systems. ISCAS 1993: 1420-1423 - 1991
- [j3]Terri S. Fiez, Guojin Liang, David J. Allstot:
Switched-current circuit design issues. IEEE J. Solid State Circuits 26(3): 192-202 (1991) - 1990
- [j2]Terri S. Fiez, David J. Allstot:
CMOS switched-current ladder filters. IEEE J. Solid State Circuits 25(6): 1360-1367 (1990)
1980 – 1989
- 1989
- [j1]Terri S. Fiez, Howard C. Yang, John J. Yang, Choung Yu, David J. Allstot:
A family of high-swing CMOS operational amplifiers. IEEE J. Solid State Circuits 24(6): 1683-1687 (1989)
Coauthor Index
[j50] [j49] [j48] [c64] [c63] [j47] [c62] [c61] [c60] [j45] [c59] [j43] [c58] [c56] [j41] [j40] [j38] [c54] [j37] [j36] [j35] [c52] [j34] [c50] [c47] [j32] [j31] [c46] [c45] [c44] [c43] [c41] [c40] [j29] [j28] [j27] [j26] [c39] [c37] [c36] [j25] [j24] [j23] [j22] [c35] [j18] [c34] [c33] [c32] [c31] [c30] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [j12] [c14] [c12]
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