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2020 – today
- 2024
[c21]Yasufumi Sakai, Naoki Matsumura, Atsuki Inoue, Hiroshi Kawaguchi, Thang Dang, Atsushi Ishikawa, Árni Björn Höskuldsson, Egill Skúlason:
Active Learning for Graph Neural Networks Training in Catalyst Energy Prediction. IJCNN 2024: 1-8- 2023
- [c20]Kengo Matsumoto, Tomoya Matsuda, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai:
A Mixed-Precision Quantization Method without Accuracy Degradation Using Semilayers. ACML 2023: 882-894 - [c19]Tomoya Matsuda, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi
, Yasufumi Sakai:
Semilayer-Wise Partial Quantization Without Accuracy Degradation or Back Propagation. ICANN (9) 2023: 283-295 - [c18]Yasufumi Sakai, Thang Dang, Shigeki Fukuta, Koichi Shirahata, Atsushi Ishikawa, Atsuki Inoue, Hiroshi Kawaguchi, Árni Björn Höskuldsson, Egill Skúlason:
Self-Supervised Learning with Atom Replacement for Catalyst Energy Prediction by Graph Neural Networks. INNS DLIA@IJCNN 2023: 458-467 - 2022
- [c17]Kazuki Okado, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai:
Channel-wise quantization without accuracy degradation using Δloss analysis. ICMLT 2022: 56-61 - [c16]Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru, Atsuki Inoue, Hiroshi Kawaguchi:
Automatic Pruning Rate Derivation for Structured Pruning of Deep Neural Networks. ICPR 2022: 2561-2567 - 2021
- [c15]Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai, Fuyuka Yamada:
Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization. ACML 2021: 886-901 - [c14]Koji Tsuru, Atsuki Inoue:
Real-time concentration measurement through forehead cerebral blood flow dynamics using NIRS. BCI 2021: 1-6 - [c13]Fuyuka Yamada, Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai:
A High-Speed Neural Architecture Search Considering the Number of Weights. KI 2021: 109-115
2010 – 2019
- 2019
- [c12]Yukito Tsunoda, Takahiro Notsu, Yasufumi Sakai, Naoki Hamada, Toshihiko Mori, Teruo Ishihara, Atsuki Inoue:
Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design. GECCO (Companion) 2019: 405-406 - 2018
- [c11]Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue:
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. ICECS 2018: 673-676 - 2017
- [c10]Atsuki Inoue, Dennis Sylvester, Edith Beigné:
Session 20 overview: Digital voltage regulators and low-power techniques. ISSCC 2017: 334-335 - [c9]Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue:
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. MLSP 2017: 1-6 - 2016
- [c8]Dejan Markovic, Antoine Dupret, Atsuki Inoue:
ES2: Computing architectures paving the path to power efficiency. ISSCC 2016: 517 - 2015
- [c7]Atsuki Inoue, Jinuk Luke Shin:
Session 4 overview: Processors: High-performance digital subcommittee. ISSCC 2015: 68-69 - 2013
- [c6]Anthony Hill, Atsuki Inoue:
Session 14 overview: Digital PLLs and building blocks. ISSCC 2013: 246-247 - 2012
- [c5]Atsuki Inoue:
Comparison between power gating and DVFS from the viewpoint of energy efficiency. ISQED 2012: 601-608 - [c4]Atsuki Inoue, Masaitsu Nakajima:
Vision for future television. ISSCC 2012: 517 - 2011
- [c3]Atsuki Inoue:
Design constraint of fine grain supply voltage control LSI. ASP-DAC 2011: 760-765
2000 – 2009
- 2009
- [j1]Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue:
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support. IEEE J. Solid State Circuits 44(4): 1178-1183 (2009) - 2007
- [c2]Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata:
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. ISSCC 2007: 290-603 - 2006
- [c1]Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga:
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. ASP-DAC 2006: 541-546
Coauthor Index
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