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2020 – today
- 2024
[j87]Koh Watanabe
, Ryota Sakai, Satoshi Tanaka, Makoto Nagata, Hideki Osaka, Atsushi Nakamura, Ifong Wu, Yasushi Matsumoto, Kaoru Gotoh:
Electromagnetic Interference With the Mobile Communication Devices in Unmanned Aerial Vehicles and Its Countermeasures. IEEE Access 12: 11642-11652 (2024)- [c100]Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata:
On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. COSADE 2024: 22-37 - [c99]Takuya Wadatsumi, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Lang Lin, Norman Chang, Makoto Nagata:
Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection. EMC Compo 2024: 1-4 - [c98]Hiraku Uehara, Koh Watanabe, Sosuke Ashida, Yushi Mitsuya, Satoshi Tanaka, Makoto Nagata:
Accuracy of GPS Positioning Measurements in response to Electromagnetic Noise Characteristics. EMC Compo 2024: 116-118 - [c97]Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata:
Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips. FDTC 2024: 44-52 - [c96]Henian Li, Lang Lin, Norman Chang, Sreeja Chowdhury, Dylan Mcguire, Bozidar Novakovic, Kazuki Monta, Makoto Nagata, Ying-Shiun Li, Pramod M. S, Piin-Chen Yeh, Jyh-Shing Roger Jang, Chengjie Xi, Qiutong Jin, Navid Asadi, Mark M. Tehranipoor:
Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation. HOST 2024: 107-111 - [c95]Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Akhilesh Kumar, Norman Chang:
Si-Backside Side-Channel Leakage Measurement and Simulation. ISOCC 2024: 189-190 - 2023
- [j86]Makoto Nagata:
Design of Circuits and Packaging Systems for Security Chips. IEICE Trans. Electron. 106(7): 345-351 (2023) - [j85]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata:
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. IEICE Trans. Electron. 106(10): 556-564 (2023) - [j84]Ryozo Takahashi, Takuji Miki, Makoto Nagata:
An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. IEICE Trans. Electron. 106(10): 565-569 (2023) - [j83]Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata:
Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis. ACM J. Emerg. Technol. Comput. Syst. 19(1): 9:1-9:23 (2023) - [j82]Makoto Nagata, Massimo Alioto:
Guest Editorial IEEE 2022 European Solid-State Circuits Conference. IEEE J. Solid State Circuits 58(7): 1823-1824 (2023) - [c94]Kazuki Monta, Makoto Nagata, Josep Balasch, Ingrid Verbauwhede:
On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits. DAC 2023: 1-6 - [c93]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata:
Characterization of Backside ESD Impacts on Integrated Circuits. IRPS 2023: 1-6 - [c92]Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. ISSCC 2023: 216-217 - [c91]Tom Kocmi, Eleftherios Avramidis, Rachel Bawden, Ondrej Bojar, Anton Dvorkovich, Christian Federmann, Mark Fishel, Markus Freitag, Thamme Gowda, Roman Grundkiewicz, Barry Haddow, Philipp Koehn, Benjamin Marie, Christof Monz, Makoto Morishita, Kenton Murray, Makoto Nagata, Toshiaki Nakazawa, Martin Popel, Maja Popovic, Mariya Shmatova:
Findings of the 2023 Conference on Machine Translation (WMT23): LLMs Are Here but Not Quite There Yet. WMT 2023: 1-42 - 2022
- [j81]Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen:
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test 39(5): 79-87 (2022) - [j80]Takuji Miki, Ryozo Takahashi, Makoto Nagata:
An 11-bit 0.008mm2 charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays. IEICE Electron. Express 19(8): 20220099 (2022) - [j79]Makoto Nagata, Takuji Miki, Noriyuki Miura:
Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 5-14 (2022) - [c90]Makoto Nagata:
Exploring Fault Injection Attack Resilience of Secure IC Chips : Invited Paper. IRPS 2022: 11 - [c89]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo:
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. IRPS 2022: 14-1 - 2021
- [j78]Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18(9): 20210070 (2021) - [j77]Makoto Nagata:
Foreword. IEICE Trans. Electron. 104-C(7): 261 (2021) - [j76]Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata:
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. 11(3): 289-298 (2021) - [j75]Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma:
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - [c88]Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen:
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS 2021: 1-4 - [c87]Lang Lin, Deqi Zhu, Jimin Wen, Hua Chen, Yu Lu, Norman Chang, Calvin Chow, Harsh Shrivastav, Chia-Wei Chen, Kazuki Monta, Makoto Nagata:
Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification. HOST 2021: 270-280 - [c86]Makoto Nagata:
Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited). SLIP 2021: 24 - 2020
- [j74]Makoto Nagata:
Foreword. IEICE Trans. Electron. 103-C(4): 131 (2020) - [j73]Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata:
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. 103-C(10): 497-504 (2020) - [j72]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020) - [j71]Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020) - [j70]Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata:
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 14-18 (2020) - [c85]Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata:
A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS 2020: 1 - [c84]Lang Lin, Dinesh Selvakumaran, Deqi Zhu, Norman Chang, Calvin Chow, Makoto Nagata, Kazuki Monta:
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis. iSES 2020: 133-138
2010 – 2019
- 2019
- [j69]Takuji Miki, Noriyuki Miura, Makoto Nagata:
A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. IEICE Trans. Electron. 102-C(7): 530-537 (2019) - [j68]Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata:
Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. 90: 63-71 (2019) - [j67]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c83]Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c82]Makoto Nagata:
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. ASICON 2019: 1-4 - [c81]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - [c80]Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki:
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS 2019: 95-100 - [c79]Makoto Nagata, Takuji Miki, Noriyuki Miura:
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC 2019: 1-6 - [c78]Makoto Nagata:
Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security - Invited Paper. SPACE 2019: 1-4 - 2018
- [j66]Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne:
A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express 15(13): 20180460 (2018) - [j65]Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata:
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits 53(10): 2889-2897 (2018) - [j64]Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura:
A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. IEEE J. Solid State Circuits 53(11): 3174-3182 (2018) - [j63]Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto:
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1320-1324 (2018) - [c77]Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata:
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD 2018: 508-515 - [c76]Patrick P. Mercier, Long Yan, Makoto Nagata:
Session 17 overview: Technologies for health and society: Technology directions subcommittee. ISSCC 2018: 280-281 - [c75]Jan Genoe, Frederic Gianesello, Makoto Nagata:
Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. ISSCC 2018: 342-343 - [c74]Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura:
A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. ISSCC 2018: 352-354 - [c73]Shinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata:
Session 30 overview: Emerging memories: Memory and technology directions subcommittees. ISSCC 2018: 476-477 - [c72]Naveen Verma, Fatih Hamzaoglu, Makoto Nagata, Leland Chang:
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. ISSCC 2018: 486-487 - 2017
- [j62]Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama:
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14(2): 20162005 (2017) - [j61]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata:
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. 100-C(6): 560-567 (2017) - [j60]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki:
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30(2): 373-391 (2017) - [j59]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c71]Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata:
An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC 2017: 39-40 - [c70]Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata:
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC 2017: 25-28 - [c69]Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata:
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC 2017: 49-56 - [c68]Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata:
15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure. ISSCC 2017: 270-271 - 2016
- [c67]Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger:
PLL to the rescue: a novel EM fault countermeasure. DAC 2016: 90:1-90:6 - [c66]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata:
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC 2016: 141-144 - [c65]Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata:
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC 2016: 102-113 - [c64]Kohei Matsuda, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Tatsuya Fujii, Kazuo Sakiyama:
On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST 2016: 1-6 - [c63]Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata:
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC 2016: 492-494 - [i2]Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger:
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. 2016: 522 (2016) - 2015
- [j58]Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda:
In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. IEEE Des. Test 32(6): 87-98 (2015) - [j57]Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata:
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50(11): 2741-2749 (2015) - [j56]Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki:
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1429-1438 (2015) - [j55]Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata:
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2347-2351 (2015) - [c62]Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata:
Nano-Function materials for TSV technologies. 3DIC 2015: TS5.3.1-TS5.3.6 - [c61]Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata:
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC 2015: 26-27 - [c60]Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger:
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC 2015: 749-754 - [c59]Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki:
EM attack sensor: concept, circuit, and design-automation methodology. DAC 2015: 176:1-176:6 - [c58]Satoshi Tanaka, Peng Fan, Jingyan Ma, Hanae Aoki, Masahiro Yamaguchi, Makoto Nagata, Sho Muroga:
Analysis of on-chip digital noise coupling path for wireless communication IC test chip. EMC Compo 2015: 216-221 - [c57]Shuichi Ohno, Yuji Wakasa, Makoto Nagata:
Optimal error feedback filters for uniform quantizers at remote sensors. ICASSP 2015: 3866-3870 - [c56]Makoto Nagata, Stefano Stanzione:
Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee. ISSCC 2015: 356-357 - [c55]Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata:
At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS 2015: 1-6 - 2014
- [j54]Takefumi Yoshikawa, Makoto Nagata:
Timing margin enhancement technique for current mode interface. IEICE Electron. Express 11(19): 20140766 (2014) - [j53]Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata:
AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model. IEICE Trans. Electron. 97-C(4): 264-271 (2014) - [j52]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger:
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [j51]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [j50]Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi:
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. 97-C(6): 546-556 (2014) - [j49]Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata:
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. IEICE Trans. Electron. 97-C(6): 557-565 (2014) - [j48]Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu:
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 49(12): 2743-2747 (2014) - [c54]Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata:
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC 2014: 225-228 - [c53]Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura:
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS 2014: 258-262 - [c52]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki:
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES 2014: 1-16 - [c51]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c50]Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger:
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST 2014: 32-37 - [c49]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - [c48]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - [c47]Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata:
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT 2014: 1-4 - [c46]Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata:
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC 2014: 1-2 - [i1]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki:
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014: 541 (2014) - 2013
- [j47]Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata:
Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits. IEICE Trans. Electron. 96-C(4): 538-545 (2013) - [j46]Naoya Azuma, Makoto Nagata:
Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components. IEICE Trans. Electron. 96-C(6): 875-883 (2013) - [j45]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. 96-C(6): 884-893 (2013) - [j44]Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata:
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2516-2523 (2013) - [j43]Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata:
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2533-2541 (2013) - [c45]Satoshi Takaya, Makoto Nagata, Hiroaki Ikeda:
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. 3DIC 2013: 1-4 - [c44]Makoto Nagata, Shunsuke Shimazaki, Naoya Azuma, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi:
Measurement-based diagnosis of wireless communication performance in the presence of in-band interferers in RF ICs. EMC Compo 2013: 37-41 - [c43]Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi:
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo 2013: 42-46 - [c42]Sho Muroga, Y. Shimada, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, Naoya Azuma, Makoto Nagata, Motoki Murakami, Kazuaki Hori, Satoru Takahashi:
In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film. EMC Compo 2013: 47-52 - [c41]Akitaka Murata, Shuji Agatsuma, Daisaku Ikoma, Kouji Ichikawa, Takahiro Tsuda, Makoto Nagata, Kumpei Yoshikawa, Yuuki Araga, Yuji Harada:
Noise analysis using on-chip waveform monitor in bandgap voltage references. EMC Compo 2013: 226-231 - [c40]Kumpei Yoshikawa, Yuji Harada, Noriyuki Miura, Noriaki Takeda, Yoshiyuki Saito, Makoto Nagata:
Immunity evaluation of inverter chains against RF power on power delivery network. EMC Compo 2013: 232-237 - [c39]Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda:
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. ISSCC 2013: 434-435 - [c38]Naoya Azuma, T. Makita, S. Ueyama, Makoto Nagata, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi:
In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers. ITC 2013: 1-9 - 2012
- [j42]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. IEICE Trans. Electron. 95-C(1): 137-145 (2012) - [j41]Makoto Nagata:
Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 430-438 (2012) - [j40]Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata:
Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. IEICE Trans. Electron. 95-C(4): 586-593 (2012) - [j39]Makoto Nagata:
Foreword. IEICE Trans. Electron. 95-C(6): 977 (2012) - [j38]Kumpei Yoshikawa, Yuta Sasaki, Kouji Ichikawa, Yoshiyuki Saito, Makoto Nagata:
Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2284-2291 (2012) - [j37]Makoto Nagata, Vivek De:
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 47(4): 795-796 (2012) - [c37]Ajith Amerasekera, Makoto Nagata:
Foreword. VLSIC 2012: 1-2 - 2011
- [j36]Yoji Bando, Makoto Nagata:
Microprocessor power noise measurements with different levels of resource occupancy. IEICE Electron. Express 8(3): 182-188 (2011) - [j35]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. 94-C(4): 495-503 (2011) - [j34]Takushi Hashida, Yuuki Araga, Makoto Nagata:
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Trans. Electron. 94-C(6): 1016-1023 (2011) - [j33]Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. 94-C(6): 1024-1031 (2011) - [j32]Takushi Hashida, Makoto Nagata:
An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. IEEE J. Solid State Circuits 46(4): 789-796 (2011) - [c36]Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne:
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6 - [c35]Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh:
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92 - [c34]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61 - [c33]Takushi Hashida, Yuuki Araga, Makoto Nagata:
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS 2011: 70-75 - 2010
- [j31]Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata:
Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 440-447 (2010) - [j30]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. 93-C(6): 820-826 (2010) - [j29]Takushi Hashida, Makoto Nagata:
Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails. IEICE Trans. Electron. 93-C(6): 842-848 (2010) - [c32]Yuuki Araga, Takushi Hashida, Makoto Nagata:
An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS 2010: 3557-3560
2000 – 2009
- 2009
- [j28]Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata:
Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. IEICE Trans. Electron. 92-C(4): 475-482 (2009) - [c31]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC 2009: 187-190 - [c30]Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata:
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. CICC 2009: 219-222 - 2008
- [j27]Kouji Ichikawa, Yuki Takahashi, Yukihiko Sakurai, Takahiro Tsuda, Isao Iwase, Makoto Nagata:
Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation. IEICE Trans. Electron. 91-C(6): 936-944 (2008) - [j26]Takefumi Yoshikawa, Tetsuhiro Ogino, Makoto Nagata:
Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications. IEICE Trans. Electron. 91-C(9): 1453-1462 (2008) - [c29]Makoto Nagata, Steven L. Garverick:
Session 13 - Biomedical, sensors and MEMS. CICC 2008 - 2007
- [j25]Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 380-387 (2007) - [j24]Masao Morimoto, Makoto Nagata, Kazuo Taki:
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Trans. Electron. 90-C(4): 675-682 (2007) - [j23]Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata:
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. 90-C(4): 692-698 (2007) - [j22]Koichiro Noguchi, Takushi Hashida, Makoto Nagata:
On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. IEICE Trans. Electron. 90-C(6): 1189-1196 (2007) - [j21]Kouji Ichikawa, Yuki Takahashi, Makoto Nagata:
Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements. IEICE Trans. Electron. 90-C(6): 1282-1290 (2007) - [j20]Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki:
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. IEICE Trans. Electron. 90-C(6): 1299-1303 (2007) - [j19]Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2651-2660 (2007) - [j18]Koichiro Noguchi, Makoto Nagata:
An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1101-1110 (2007) - [c28]Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. CICC 2007: 849-852 - [c27]Makoto Nagata:
On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. DAC 2007: 400-403 - [c26]Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata:
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. ISSCC 2007: 288-603 - [c25]Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata:
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. ISSCC 2007: 290-603 - 2006
- [j17]Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki:
Communication Scheme for a Highly Collision-Resistive RFID System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 408-415 (2006) - [j16]Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata:
Multi-Ported Register File for Reducing the Impact of PVT Variation. IEICE Trans. Electron. 89-C(3): 356-363 (2006) - [j15]Koichiro Noguchi, Makoto Nagata:
An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity. IEICE Trans. Electron. 89-C(6): 761-768 (2006) - [j14]Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Trans. Electron. 89-C(11): 1535-1543 (2006) - [j13]Mitsuya Fukazawa, Makoto Nagata:
Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. IEICE Trans. Electron. 89-C(11): 1559-1566 (2006) - [j12]Yohei Fukumizu, Makoto Nagata, Kazuo Taki:
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. IEICE Trans. Electron. 89-C(11): 1581-1590 (2006) - [j11]Ali Afzali-Kusha, Makoto Nagata, Nishath K. Verghese, David J. Allstot:
Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation. Proc. IEEE 94(12): 2109-2138 (2006) - [c24]Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki:
A built-in power supply noise probe for digital LSIs. ASP-DAC 2006: 106-107 - [c23]Daisuke Kosaka, Makoto Nagata:
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. ASP-DAC 2006: 677-682 - [c22]Mitsuya Fukazawa, Makoto Nagata:
Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform. CICC 2006: 865-868 - 2005
- [j10]Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa:
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. IEICE Trans. Electron. 88-C(4): 589-596 (2005) - [j9]Masao Morimoto, Makoto Nagata, Kazuo Taki:
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Trans. Electron. 88-C(10): 2001-2008 (2005) - [j8]Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki:
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3324-3331 (2005) - [j7]Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics 17(4): 378-386 (2005) - [j6]Makoto Nagata, Takeshi Okumoto, Kazuo Taki:
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. IEEE J. Solid State Circuits 40(4): 813-819 (2005) - [c21]Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa:
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. CICC 2005: 31-34 - [c20]Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata:
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC 2005: 35-38 - [c19]Koichiro Noguchi, Makoto Nagata:
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. DATE 2005: 146-151 - [c18]Koichiro Noguchi, Makoto Nagata:
An on-chip multi-channel waveform monitor for mixed-signal VLSI diagnostics. ESSCIRC 2005: 295-298 - 2004
- [c17]Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang:
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. CICC 2004: 509-512 - 2003
- [c16]Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto:
A substrate noise analysis methodology for large-scale mixed-signal ICs. CICC 2003: 369-372 - 2002
- [j5]Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata:
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 381-388 (2002) - [c15]Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200 - [c14]Makoto Nagata, Takashi Morie, Atsushi Iwata:
Modeling substrate noise generation in CMOS digital integrated circuits. CICC 2002: 501-504 - [c13]Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata:
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. ASP-DAC/VLSI Design 2002: 71-76 - 2001
- [j4]Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata:
Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits 36(3): 539-549 (2001) - [j3]Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits 36(8): 1286-1290 (2001) - [c12]Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata:
Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14 - [c11]Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487 - [c10]Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata:
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122 - 2000
- [j2]Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 671-678 (2000) - [c9]Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata:
A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20 - [c8]Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata:
An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24 - [c7]Makoto Nagata, Atsushi Iwata:
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC 2000: 623-630 - [c6]Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC 2000: 95-98 - [c5]Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie:
Pulse modulation circuit architecture and its application to functional image sensors. ISCAS 2000: 301-304
1990 – 1999
- 1999
- [c4]Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata:
Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC 1999: 575-578 - [c3]Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie:
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88 - 1998
- [j1]Makoto Nagata, Jun Funakoshi, Atsushi Iwata:
A PWM signal processing core circuit based on a switched current integration technique. IEEE J. Solid State Circuits 33(1): 53-60 (1998) - [c2]Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata:
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585 - [c1]Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata:
Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589
Coauthor Index
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