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2020 – today
- 2023
[c84]Po-Yao Chuang
, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6- [c83]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - [c82]Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos:
Silent Data Errors: Sources, Detection, and Modeling. VTS 2023: 1-12 - [c81]Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty:
IP Session on Chiplet: Design, Assembly, and Test. VTS 2023: 1 - 2022
- [c80]Sreejit Chakravarty:
Special Session: A Call to Standardize Chip-let Interconnect Testing. VTS 2022: 1-3 - [e1]Luca Cassano, Sreejit Chakravarty, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022. IEEE 2022, ISBN 978-1-6654-5938-9 [contents] - 2020
- [j41]Sourav Das, Fei Su, Sreejit Chakravarty:
Testing of Prebond Through Silicon Vias. IEEE Des. Test 37(4): 27-34 (2020) - [c79]Sreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim:
Internal I/O Testing: Definition and a Solution. VTS 2020: 1-6
2010 – 2019
- 2019
- [c78]Sourav Das, Fei Su, Sreejit Chakravarty:
A Comparative Study of Pre-bond TSV Test Methodologies. VTS 2019: 1-6 - 2018
- [c77]Sourav Das, Fei Su, Sreejit Chakravarty:
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing. ITC 2018: 1-10 - [c76]M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla:
Innovative practices on memory test practice. VTS 2018: 1 - [c75]Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti:
Innovative practices on functional testing and fault simulation for FuSa. VTS 2018: 1 - 2017
- [c74]Prashant Goteti, Sreejit Chakravarty:
Innovative practices session 6C DFT for functional safety. VTS 2017: 1 - 2016
- [j40]Sreejit Chakravarty, Ranjeeta Bisoi, P. K. Dash:
A Hybrid Kernel Extreme Learning Machine and Improved Cat Swarm Optimization for Microarray Medical Data Classification. Int. J. Appl. Evol. Comput. 7(3): 71-100 (2016) - [j39]Sreejit Chakravarty, P. Mohapatra, Pradipta Kishore Dash:
Evolutionary extreme learning machine for energy price forecasting. Int. J. Knowl. Based Intell. Eng. Syst. 20(2): 75-96 (2016) - [j38]P. Mohapatra, Sreejit Chakravarty, P. K. Dash:
Microarray medical data classification using kernel ridge regression and modified cat swarm optimization based gene selection system. Swarm Evol. Comput. 28: 144-160 (2016) - 2015
- [j37]P. Mohapatra, Sreejit Chakravarty, Pradipta K. Dash:
An improved cuckoo search based extreme learning machine for medical data classification. Swarm Evol. Comput. 24: 25-49 (2015) - 2014
- [c73]Fan Yang, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning:
Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests. ATS 2014: 101-106 - 2013
- [j36]Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-safe application of tdf patterns to flip-chip designs during wafer test. ACM Trans. Design Autom. Electr. Syst. 18(3): 43:1-43:20 (2013) - [c72]Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene:
Innovative practices session 2C: Memory test. VTS 2013: 1 - 2012
- [j35]Sreejit Chakravarty, Pradipta K. Dash:
A PSO based integrated functional link net and interval type-2 fuzzy logic system for predicting stock market indices. Appl. Soft Comput. 12(2): 931-941 (2012) - [j34]Sreejit Chakravarty, Pradipta K. Dash:
Evolutionary functional link interval type-2 fuzzy neural system for exchange rate prediction. Int. J. Data Min. Model. Manag. 4(4): 384-412 (2012) - [j33]Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty:
Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits. J. Low Power Electron. 8(2): 235-247 (2012) - [j32]Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen:
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electron. 8(2): 248-258 (2012) - [c71]Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li:
Silicon evaluation of faster than at-speed transition delay tests. VTS 2012: 80-85 - [c70]Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor:
A novel method for fast identification of peak current during test. VTS 2012: 191-196 - 2011
- [j31]Sreejit Chakravarty, Pradipta K. Dash:
Dynamic filter weights neural network model integrated with differential evolution for day-ahead price forecasting in energy market. Expert Syst. Appl. 38(9): 10974-10982 (2011) - [j30]Sreejit Chakravarty, Pradipta K. Dash, V. Ravikumar Pandi, Bijaya K. Panigrahi:
An Evolutionary Functional Link Neural Fuzzy Model for Financial Time Series Forecasting. Int. J. Appl. Evol. Comput. 2(3): 39-58 (2011) - [c69]Sreejit Chakravarty:
A Process Monitor Based Speed Binning and Die Matching Algorithm. Asian Test Symposium 2011: 311-316 - [c68]Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas:
Optimal manufacturing flow to determine minumum operating voltage. ITC 2011: 1-10 - [c67]Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-safe test application using an effective gating approach considering current limits. VTS 2011: 160-165 - 2010
- [c66]Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. Asian Test Symposium 2010: 301-306 - [c65]Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh:
Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium 2010: 367-370 - [c64]Fan Yang, Sreejit Chakravarty:
Testing of latch based embedded arrays using scan tests. ITC 2010: 104-113 - [c63]Sean H. Wu, Sreejit Chakravarty, Li-C. Wang:
Impact of multiple input switching on delay test under process variation. VTS 2010: 87-92 - [c62]Sreejit Chakravarty:
Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. VTS 2010: 350
2000 – 2009
- 2009
- [j29]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty:
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 697-708 (2009) - [c61]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683 - [c60]Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum:
Path selection for monitoring unexpected systematic timing effects. ASP-DAC 2009: 781-786 - [c59]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Improving the Detectability of Resistive Open Faults in Scan Cells. DFT 2009: 383-391 - [c58]Sreejit Chakravarty, Pradipta K. Dash:
Forecasting Stock Market Indices using Hybrid Network. NaBIC 2009: 1225-1230 - 2008
- [j28]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electron. Test. 24(1-3): 259-269 (2008) - [c57]Sean H. Wu, Sreejit Chakravarty, Alexander Tetelbaum, Li-C. Wang:
Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay. ATS 2008: 142-144 - [c56]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402 - [c55]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
An Enhanced Logic BIST Architecture for Online Testing. IOLTS 2008: 10-15 - [c54]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Internal Stuck-open Faults in Scan Chains. ITC 2008: 1-10 - [c53]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS 2008: 79-84 - [c52]I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty:
An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402 - 2006
- [j27]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2954-2964 (2006) - [c51]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
An Approach to Minimizing Functional Constraints. DFT 2006: 215-226 - [c50]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Exact At-speed Delay Fault Grading in Sequential Circuits. ITC 2006: 1-10 - [c49]Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty:
A Study of Implication Based Pseudo Functional Testing. ITC 2006: 1-10 - [c48]Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23 - [c47]Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty:
Silicon Evaluation of Logic Proximity Bridge Patterns. VTS 2006: 78-85 - 2005
- [j26]Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Efficient techniques for transition testing. ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005) - [c46]Sreejit Chakravarty:
Improving Logic Test Quality of Microprocessors. Asian Test Symposium 2005 - [c45]Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium 2005: 194-201 - [c44]Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE 2005: 990-995 - [c43]Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty:
Logic proximity bridges. ITC 2005: 10 - [c42]Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee:
Transition Tests for High Performance Microprocessors. VTS 2005: 29-34 - [c41]Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee:
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. VTS 2005: 337-342 - 2004
- [j25]Sujit T. Zachariah, Sreejit Chakravarty:
Extraction of two-node bridges from large industrial circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 433-439 (2004) - [c40]Sreejit Chakravarty, Eric W. Savage, Eric N. Tran:
Defect Coverage Analysis of Partitioned Testing. ITC 2004: 907-915 - [c39]Manan Syal, Michael S. Hsiao, Sreejit Chakravarty:
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ITC 2004: 1034-1043 - 2003
- [j24]Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. J. Electron. Test. 19(4): 437-445 (2003) - [j23]Sujit T. Zachariah, Sreejit Chakravarty:
Algorithm to extract two-node bridges. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 741-744 (2003) - [c38]Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty:
Efficient Implication - Based Untestable Bridge Fault Identifier. VTS 2003: 393-402 - 2002
- [c37]Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Novel ATPG algorithms for transition faults. ETW 2002: 47-52 - [c36]Sreejit Chakravarty:
Supplemental Test Methods (Tutorial Abstract). ISQED 2002: 7 - [c35]Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah:
Experimental Evaluation of Scan Tests for Bridges. ITC 2002: 509-518 - [c34]Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Techniques to Reduce Data Volume and Application Time for Transition Test. ITC 2002: 983-992 - [c33]Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah:
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. VTS 2002: 367-372 - [c32]Sreejit Chakravarty, Ankur Jain:
Fault Models for Speed Failures Caused by Bridges and Opens. VTS 2002: 373-378 - 2001
- [j22]Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty:
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001) - [j21]Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
Automatic generation and compaction of March tests for memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 845-857 (2001) - [c31]Sujit T. Zachariah, Sreejit Chakravarty:
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. VLSI Design 2001: 333-338 - 2000
- [j20]Sreejit Chakravarty, Sujit T. Zachariah:
STBM: a fast algorithm to simulate IDDQ tests forleakage faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 568-576 (2000) - [c30]Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth:
A novel algorithm to extract two-node bridges. DAC 2000: 790-793 - [c29]Sujit T. Zachariah, Sreejit Chakravarty:
A scalable and efficient methodology to extract two node bridges from large industrial circuits. ITC 2000: 750-759 - [c28]Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method. ITC 2000: 1060-1069
1990 – 1999
- 1999
- [c27]Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu:
On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406 - [c26]Sujit T. Zachariah, Sreejit Chakravarty:
A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. VLSI Design 1999: 91-94 - [c25]Sreejit Chakravarty, Vinodh Gopal:
Techniques to Encode and Compress Fault Dictionaries. VTS 1999: 195-200 - 1998
- [j19]Yiming Gong, Sreejit Chakravarty:
Locating bridging faults using dynamically computed stuck-at fault dictionaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 876-887 (1998) - [j18]Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1325-1333 (1998) - [c24]Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty:
A new framework for generating optimal March tests for memory arrays. ITC 1998: 73-82 - [c23]Vinay Dabholkar, Sreejit Chakravarty:
Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391 - 1997
- [j17]Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel:
Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997) - [c22]Vinay Dabholkar, Sreejit Chakravarty:
Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148 - [c21]Sreejit Chakravarty:
On the capability of delay tests to detect bridges and opens. Asian Test Symposium 1997: 314-319 - [c20]Yiming Gong, Sreejit Chakravarty:
Using fault sampling to compute IDDQ diagnostic test set. VTS 1997: 74-79 - 1996
- [j16]Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman:
Diagnostic simulation of stuck-at faults in combinational circuits. J. Electron. Test. 8(1): 87-97 (1996) - [j15]Sreejit Chakravarty, Paul J. Thadikaran:
Algorithms to select IDDQ measurement points to detect bridging faults. J. Electron. Test. 8(3): 275-285 (1996) - [j14]Sreejit Chakravarty:
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. IEEE Trans. Computers 45(8): 985-991 (1996) - [j13]Sreejit Chakravarty, Paul J. Thadikaran:
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. IEEE Trans. Computers 45(10): 1131-1140 (1996) - [c19]Paul J. Thadikaran, Sreejit Chakravarty:
Fast Algorithms for Computer IDDQ Tests for Combination Circuits. VLSI Design 1996: 103-106 - [c18]Sreejit Chakravarty:
A sampling technique for diagnostic fault simulation. VTS 1996: 192-197 - 1995
- [j12]Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois:
Conference Reports. IEEE Des. Test Comput. 12(4): 95-97 (1995) - [c17]Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel:
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138 - [c16]Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel:
Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349 - [c15]Yiming Gong, Sreejit Chakravarty:
On adaptive diagnostic test generation. ICCAD 1995: 181-184 - [c14]Sreejit Chakravarty, Yiming Gong:
Voting model based diagnosis of bridging faults in combinational circuits. VLSI Design 1995: 338-342 - [c13]Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel:
Cyclic stress tests for full scan circuits. VTS 1995: 89-94 - 1994
- [c12]Sreejit Chakravarty, Paul J. Thadikaran:
A Study of IDDQ Subset Selection Algorithms for Bridging Faults. ITC 1994: 403-412 - [c11]Sreejit Chakravarty, Sivaprakasam Suresh:
IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. VLSI Design 1994: 179-182 - [c10]Sreejit Chakravarty, Yiming Gong:
Diagnostic simulation of stuck-at faults in combinational circuits. VTS 1994: 128-133 - 1993
- [j11]Sreejit Chakravarty:
A Characterization of Binary Decision Diagrams. IEEE Trans. Computers 42(2): 129-137 (1993) - [c9]Sreejit Chakravarty, Yiming Gong:
An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. DAC 1993: 520-524 - [c8]Sreejit Chakravarty, Paul J. Thadikaran:
Simulation and generation of IDDQ tests for bridging faults in combinational circuits. VTS 1993: 25-32 - 1992
- [j10]Sreejit Chakravarty, Minsheng Liu:
Algorithms for IDDQ measurement based diagnosis of bridging faults. J. Electron. Test. 3(4): 377-385 (1992) - [j9]Sreejit Chakravarty, Ajay Shekhawat:
Parallel and serial heuristics for the minimum set cover problem. J. Supercomput. 5(4): 331-345 (1992) - [c7]Sreejit Chakravarty, Minsheng Liu:
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. DAC 1992: 353-356 - [c6]Sreejit Chakravarty:
On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets. VLSI Design 1992: 49-54 - 1991
- [j8]Sreejit Chakravarty:
A characterization of robust test-pairs for stuck-open faults. J. Electron. Test. 1(4): 275-286 (1991) - [j7]Sreejit Chakravarty, Xin He, S. S. Ravi:
Minimum area layout of series-parallel transistor networks is NP-hard. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7): 943-949 (1991) - 1990
- [j6]Sreejit Chakravarty:
Testing of non-feedback bridging faults. Integr. 9(2): 109-127 (1990) - [j5]Sreejit Chakravarty, Harry B. Hunt III:
On Computing Signal Probability and Detection Probability of Stuck-at Faults. IEEE Trans. Computers 39(11): 1369-1377 (1990) - [j4]Sreejit Chakravarty, S. S. Ravi:
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 329-331 (1990) - [c5]Sreejit Chakravarty:
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). DAC 1990: 736-739 - [c4]Ajay Shekhawat, Sreejit Chakravarty:
Heuristics for the MSC Problem for Serial and Shared-Memory Computers. ICPP (3) 1990: 64-67
1980 – 1989
- 1989
- [j3]Sreejit Chakravarty, Harry B. Hunt III:
A Note on Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 38(6): 861-864 (1989) - [j2]Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz:
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. IEEE Trans. Computers 38(6): 865-869 (1989) - [j1]Sreejit Chakravarty:
On the complexity of computing tests for CMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 973-980 (1989) - [c3]Sreejit Chakravarty:
A Testable Realization of CMOS Combinational Circuits. ITC 1989: 509-518 - 1988
- [c2]Sreejit Chakravarty, Shambhu J. Upadhyaya:
A Unified Approach to Designing Fault-Tolerant Processor Ensembles. ICPP (1) 1988: 339-342 - 1986
- [c1]Sreejit Chakravarty, Harry B. Hunt III:
On the Computation of Detection Probability for Multiple Faults. ITC 1986: 252-262
Coauthor Index
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