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2020 – today
- 2021
[j28]Ricardo Neftali Pontaza Rodas
, Ying-Dar Lin, Shih-Lien Lu, Keh-Jeng Chang:
O2MD²: A New Post-Quantum Cryptosystem With One-to-Many Distributed Key Management Based on Prime Modulo Double Encapsulation. IEEE Access 9: 109260-109288 (2021)- 2020
- [c61]Zexi Ji, Wanyeong Jung, Jongchan Woo, Khushal Sethi, Shih-Lien Lu, Anantha P. Chandrakasan:
CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays. A-SSCC 2020: 1-4
2010 – 2019
- 2019
- [j27]Shreyas Sen, Arijit Raychowdhury, Shih-Lien Lu:
Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes. IEEE Des. Test 36(2): 5-6 (2019) - [c60]Yuan-Hsi Chou, Shih-Lien Lu:
A High Performance, Low Energy, Compact Masked 128-Bit AES in 22nm CMOS Technology. VLSI-DAT 2019: 1-4 - [c59]Shih-Lien Lu, Cheng-En Lee, Peter Noel, Saman Adham, Ted Wong, Jonathan Chang:
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering. VLSI-DAT 2019: 1-4 - 2018
- [c58]Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury:
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC 2018: 1-2 - [c57]Shih-Lien Lu:
A foundry's view of hardware security. VLSI-DAT 2018: 1 - 2017
- [c56]Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu:
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC 2017: 404-405 - 2016
- [j26]Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
DRAM Refresh Mechanisms, Penalties, and Trade-Offs. IEEE Trans. Computers 65(1): 108-121 (2016) - [c55]Xi Tao, Qi Zeng, Jih-Kwon Peir, Shih-Lien Lu:
Small cache lookaside table for fast DRAM cache access. IPCCC 2016: 1-10 - [c54]Xi Tao, Qi Zeng, Jih-Kwon Peir, Shih-Lien Lu:
Runahead Cache Misses Using Bloom Filter. PDCAT 2016: 1-6 - 2015
- [c53]Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. ISCA 2015: 235-246 - [c52]Paul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. MEMSYS 2015: 179-190 - [c51]Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang:
Improving DRAM latency with dynamic asymmetric subarray. MICRO 2015: 255-266 - [c50]Shih-Lien Lu:
Evaluation methods of computer memory system. VLSI-DAT 2015: 1-4 - [c49]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu:
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2014
- [j25]Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu:
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1356-1369 (2014) - [c48]Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian:
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA 2014: 626-637 - [c47]Hui Wang, Chunrong Lai, Yicong Huang, Shih-Lien Lu, Rui Wang, Zhongzhi Luan, Depei Qian:
Remapping NUCA: Improving NUCA Cache's Power Efficiency. HPCC/CSS/ICESS 2014: 38-41 - [c46]Jih-Kwon Peir, Shih-Chang Kevin Lai, Shih-Lien Lu, Jared Stark, Konrad Lai:
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching. ICS 25th Anniversary 2014: 65-67 - [c45]Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun:
Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. SC 2014: 117-127 - 2013
- [j24]Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee:
Reducing cache and TLB power by exploiting memory region and privilege level semantics. J. Syst. Archit. 59(6): 279-295 (2013) - [c44]Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob:
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. HPCA 2013: 143-154 - [c43]Xi Tao, Yan Qiao, Jih-Kwon Peir, Shigang Chen, Zhuo Huang, Shih-Lien Lu:
Guided multiple hashing: Achieving near perfect balance for fast routing lookup. ICNP 2013: 1-10 - [c42]Jianmin Chen, Xi Tao, Zhen Yang, Jih-Kwon Peir, Xiaoyuan Li, Shih-Lien Lu:
Guided Region-Based GPU Scheduling: Utilizing Multi-thread Parallelism to Hide Memory Latency. IPDPS 2013: 441-451 - [i1]Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun:
Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. CoRR abs/1309.7321 (2013) - 2012
- [j23]Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2147-2151 (2012) - [c41]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c40]Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held:
Scaling the "Memory Wall": Designer track. ICCAD 2012: 271-272 - [c39]Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee:
Reducing L1 caches power by exploiting software semantics. ISLPED 2012: 391-396 - 2011
- [j22]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011) - [j21]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46(1): 194-208 (2011) - [j20]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46(4): 797-805 (2011) - [j19]Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu:
Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Trans. Computers 60(1): 50-63 (2011) - [j18]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 441-454 (2011) - [j17]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De:
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2017-2025 (2011) - [c38]Ilya Wagner, Shih-Lien Lu:
Distributed hardware matcher framework for SoC survivability. DATE 2011: 305-310 - [c37]Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu:
Energy-efficient cache design using variable-strength error-correcting codes. ISCA 2011: 461-472 - [c36]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Integrating formal verification and high-level processor pipeline synthesis. SASP 2011: 22-29 - 2010
- [c35]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c34]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De:
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 - [c33]Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam:
Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC 2010: 314-319 - [c32]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic pipelining from transactional datapath specifications. DATE 2010: 1001-1004 - [c31]Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA 2010: 83-93 - [c30]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 - [c29]James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 - [c28]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j16]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 44(1): 49-63 (2009) - [j15]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [j14]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu:
Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009) - [c27]Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien Lu:
Content Addressable Memory for Low-Power and High-Performance Applications. CSIE (3) 2009: 423-427 - [c26]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - [c25]James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik:
Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD 2009: 71-73 - [c24]Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra S. Yavatkar, Shih-Lien Lu, Nader Bagherzadeh:
Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793 - [c23]Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu:
Improving cache lifetime reliability at ultra-low voltages. MICRO 2009: 89-99 - 2008
- [j13]Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow:
A Desktop Computer with a Reconfigurable Pentium®. ACM Trans. Reconfigurable Technol. Syst. 1(1): 5:1-5:15 (2008) - [j12]Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu:
Active Cache Emulator. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 229-240 (2008) - [c22]Changjian Gao, Shih-Lien Lu:
Novel FPGA based Haar classifier face detection algorithm acceleration. FPL 2008: 373-378 - [c21]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu:
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214 - [c20]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - [c19]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC 2008: 402-403 - [p1]Shih-Lien Lu, Ravichandran Ramachandran:
Carry Logic. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j11]John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007) - [c18]Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh:
An FPGA-based Pentium in a complete desktop system. FPGA 2007: 53-59 - [c17]Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee:
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. FPL 2007: 47-53 - [c16]Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu:
Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332 - [c15]Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy:
Fine-Grained Redundancy in Adders. ISQED 2007: 317-321 - 2006
- [j10]Roger Morrison, Ben Lee, Shih-Lien Lu:
Asymmetric Clustering using a Register Cache. J. Instr. Level Parallelism 8 (2006) - [c14]Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu:
Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72 - [c13]David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek:
Research accelerator for multiple processors. Hot Chips Symposium 2006: 1-42 - 2005
- [c12]Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Pei-Chun Chen:
Improving branch prediction accuracy with parallel conservative correctors. Conf. Computing Frontiers 2005: 334-341 - [c11]Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De:
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC 2005: 355-358 - [c10]Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu:
Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS 2005: 12-20 - 2004
- [j9]Shih-Lien Lu:
Speeding Up Processing with Approximation Circuits. Computer 37(3): 67-73 (2004) - [c9]Chunrong Lai, Shih-Lien Lu:
Efficient Victim Mechanism on Sector Cache Organization. Asia-Pacific Computer Systems Architecture Conference 2004: 16-29 - 2003
- [j8]Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar:
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits 38(5): 755-761 (2003) - [c8]Shih-Lien Lu, Konrad Lai:
Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL 2003: 638-647 - [c7]Shih-Chang Lai, Shih-Lien Lu:
Hardware-based Pointer Data Prefetcher. ICCD 2003: 290-298 - 2002
- [c6]Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir:
Ditto Processor. DSN 2002: 525-536 - [c5]Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai:
Bloom filtering cache misses for accurate data speculation and prefetching. ICS 2002: 189-198 - [c4]Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai:
Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170 - 2001
- [j7]Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen:
Coming challenges in microarchitecture and architecture. Proc. IEEE 89(3): 325-340 (2001) - 2000
- [c3]Tong Liu, Shih-Lien Lu:
Performance improvement with circuit-level speculation. MICRO 2000: 348-355
1990 – 1999
- 1998
- [c2]Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu:
Non-Stalling CounterFlow Architecture. HPCA 1998: 334-341 - 1997
- [c1]Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller:
Advances of the Counterflow Pipeline Microarchitecture. HPCA 1997: 230-236 - 1996
- [j6]Ravichandran Ramachandran, Shih-Lien Lu:
Efficient arithmetic using self-timing. IEEE Trans. Very Large Scale Integr. Syst. 4(4): 445-454 (1996) - 1995
- [j5]Shih-Lien Lu:
Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 338-341 (1995) - [j4]Chih-Ming Chang, Shih-Lien Lu:
Design of a static MIMD data flow processor using micropipelines. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 370-378 (1995)
1980 – 1989
- 1988
- [j3]Shih-Lien Lu:
A safe single-phase clocking scheme for CMOS circuits. IEEE J. Solid State Circuits 23(1): 280-283 (1988) - [j2]Shih-Lien Lu:
Implementation of iterative networks with CMOS differential logic. IEEE J. Solid State Circuits 23(4): 1013-1017 (1988) - [j1]Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu:
Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 998-1004 (1988)
Coauthor Index
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