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ORCIDLaura Pozzi
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- affiliation: University of Lugano, Switzerland
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2020 – today
- 2024
[j28]Riccardo Felici, Laura Pozzi, Carlo A. Furia:
HyperPUT: generating synthetic faulty programs to challenge bug-finding tools. Empir. Softw. Eng. 29(2): 38 (2024)- [j27]Cristian Tirelli
, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda, David Atienza, Laura Pozzi:
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. ACM J. Emerg. Technol. Comput. Syst. 20(3): 8:1-8:26 (2024) - [i6]Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda Calero, David Atienza, Laura Pozzi:
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. CoRR abs/2402.12834 (2024) - [i5]Riccardo Felici, Laura Pozzi, Carlo A. Furia:
ShellFuzzer: Grammar-based Fuzzing of Shell Interpreters. CoRR abs/2408.00433 (2024) - 2023
- [j26]Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi:
Graph Neural Networks for High-Level Synthesis Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 28(2): 25:1-25:20 (2023) - [c47]Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi:
SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures. CF 2023: 383-384 - [c46]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF 2023: 393-394 - [c45]Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi:
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures. DATE 2023: 1-6 - [c44]Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
A Parametrizable Template for Approximate Logic Synthesis. DSN-W 2023: 175-178 - [c43]Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi:
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W 2023: 199-202 - 2022
- [j25]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 840-853 (2022) - [c42]Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi:
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. DATE 2022: 1449-1454 - [i4]Riccardo Felici, Laura Pozzi, Carlo A. Furia:
HyperPUT: Generating Synthetic Faulty Programs to Challenge Bug-Finding Tools. CoRR abs/2209.06615 (2022) - 2021
- [j24]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. IEEE Embed. Syst. Lett. 13(4): 194-197 (2021) - [j23]João M. P. Cardoso, André DeHon, Laura Pozzi:
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems. IEEE Trans. Computers 70(12): 2013-2014 (2021) - [j22]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi:
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Trans. Emerg. Top. Comput. 9(1): 35-43 (2021) - [i3]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. CoRR abs/2101.00587 (2021) - [i2]Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi:
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration. CoRR abs/2111.14767 (2021) - 2020
- [j21]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda:
Approximate Logic Synthesis: A Survey. Proc. IEEE 108(12): 2195-2213 (2020) - [j20]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3736-3747 (2020) - [c41]Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi:
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. ARC 2020: 14-29
2010 – 2019
- 2019
- [j19]Loris Duch, Soumya Basu, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza:
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. IEEE Embed. Syst. Lett. 11(2): 50-53 (2019) - [j18]Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi:
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 741-754 (2019) - [c40]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC 2019: 40 - [c39]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin:
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. DATE 2019: 948-951 - [c38]Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. ICCD 2019: 129-137 - 2018
- [c37]Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
A partitioning strategy for exploring error-resilience in circuits: work-in-progress. CASES 2018: 5:1-5:2 - [c36]Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
Circuit carving: A methodology for the design of approximate hardware. DATE 2018: 545-550 - [c35]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi:
Lattice-Traversing Design Space Exploration for High Level Synthesis. ICCD 2018: 210-217 - [c34]Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi:
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. HPCS 2018: 91-97 - [c33]Soumya Basu, Loris Duch, Miguel Peón Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi:
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. ISCAS 2018: 1-5 - 2017
- [j17]Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza:
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2448-2461 (2017) - [j16]Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza:
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. ACM Trans. Embed. Comput. Syst. 16(5s): 159:1-159:19 (2017) - 2016
- [j15]Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza:
Inexact-aware architecture design for ultra-low power bio-signal analysis. IET Comput. Digit. Tech. 10(6): 306-314 (2016) - [c32]Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi:
A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. BioCAS 2016: 416-419 - 2015
- [j14]Emanuele Giaquinta, Anadi Mishra, Laura Pozzi:
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 483-494 (2015) - 2013
- [j13]Emanuele Giaquinta, Laura Pozzi:
An Effective Exact Algorithm and a New Upper Bound for the Number of Contacts in the Hydrophobic-Polar Two-Dimensional Lattice Model. J. Comput. Biol. 20(8): 593-609 (2013) - 2012
- [j12]Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt:
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1803-1816 (2012) - 2011
- [j11]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1062-1074 (2011) - [c31]Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt:
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE 2011: 1513-1516
2000 – 2009
- 2009
- [j10]Alex Orailoglu, Laura Pozzi:
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12): 1786-1787 (2009) - [j9]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4: 230-243 (2009) - [c30]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. DATE 2009: 542-547 - 2008
- [j8]Paolo Bonzini, Laura Pozzi:
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1259-1267 (2008) - [c29]Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi:
Compiling custom instructions onto expression-grained reconfigurable architectures. CASES 2008: 51-60 - [c28]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. SASP 2008: 26-33 - 2007
- [j7]Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 435-446 (2007) - [c27]Paolo Bonzini, Laura Pozzi:
A Retargetable Framework for Automated Discovery of Custom Instructions. ASAP 2007: 334-341 - [c26]Laura Pozzi, Pierre G. Paulin:
A future of customizable processors: are we there yet? DATE 2007: 1224-1225 - [c25]Paolo Bonzini, Laura Pozzi:
Polynomial-time subgraph enumeration for automated instruction set extension. DATE 2007: 1331-1336 - [c24]Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214 - [c23]Paolo Bonzini, Dilek Harmanci, Laura Pozzi:
A Study of Energy Saving in Customizable Processors. SAMOS 2007: 304-312 - [i1]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. CoRR abs/0710.4820 (2007) - 2006
- [j6]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek:
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30(6): 334-354 (2006) - [j5]Laura Pozzi, Kubilay Atasu, Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1209-1229 (2006) - [j4]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 754-762 (2006) - [j3]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 910-915 (2006) - [c22]Paolo Bonzini, Laura Pozzi:
Code transformation strategies for extensible embedded processors. CASES 2006: 242-252 - [c21]Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217 - [c20]Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma:
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE 2006: 218-223 - [c19]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656 - 2005
- [j2]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Des. Test Comput. 22(2): 102-113 (2005) - [c18]Laura Pozzi, Paolo Ienne:
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES 2005: 2-10 - [c17]Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne:
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS 2005: 243-248 - [c16]Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251 - 2004
- [c15]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP 2004: 339-351 - [c14]Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt:
Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734 - [c13]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors. DAC 2004: 948-953 - [c12]Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne:
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE 2004: 748 - [c11]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM 2004: 24-33 - [c10]Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL 2004: 596-605 - [c9]Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32 - 2003
- [j1]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. 31(6): 411-428 (2003) - [c8]Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli:
Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP 2003: 108- - [c7]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC 2003: 256-261 - 2002
- [c6]Laura Pozzi, Miljan Vuletic, Paolo Ienne:
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE 2002: 1138 - 2001
- [c5]Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. IEEE International Workshop on Rapid System Prototyping 2001: 50-57 - 2000
- [c4]Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). FPGA 2000: 218
1990 – 1999
- 1999
- [c3]Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
A DAG-Based Design Approach for Reconfigurable VLIW Processors. DATE 1999: 778-779 - 1998
- [c2]Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami:
Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). FPGA 1998: 258 - 1997
- [c1]Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami:
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. DFT 1997: 85-93
Coauthor Index
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