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2020 – today
- 2024
[j40]Abdelrahman Hosny
, Sherief Reda:
Automatic MILP solver configuration by learning problem similarities. Ann. Oper. Res. 339(1-2): 909-936 (2024)- [j39]Manar Abdelatty, Joseph Incandela, Kangping Hu, Pushkaraj S. Joshi, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein:
Electrical Capacitance Tomography of Cell Cultures on a CMOS Microelectrode Array. IEEE Trans. Biomed. Circuits Syst. 18(4): 799-809 (2024) - [c106]Seyed Morteza Nabavinejad, Sherief Reda, Tian Guo:
MediatorDNN: Contention Mitigation for Co-Located DNN Inference Jobs. CLOUD 2024: 502-512 - [c105]Seyed Morteza Nabavinejad, Sherief Reda, Tian Guo:
FairCIM: Fair Interference Mitigation by DNN Switching for Latency-Sensitive Inference Jobs. ACSOS 2024: 71-80 - [c104]Ahmed Agiza, Mohamed Mostagir, Sherief Reda:
PoliTune: Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in Large Language Models. AIES (1) 2024: 2-12 - [c103]Marina Neseem, Conor McCullough, Randy Hsin, Chas Leichner, Shan Li, In Suk Chong, Andrew G. Howard, Lukasz Lew, Sherief Reda, Ville-Mikko Rautio, Daniele Moro:
PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks. CVPR 2024: 15996-16005 - [c102]Ahmed Agiza, Marina Neseem, Sherief Reda:
MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning. CVPR 2024: 16196-16205 - [i26]Abdelrahman Hosny, Sherief Reda:
torchmSAT: A GPU-Accelerated Approximation To The Maximum Satisfiability Problem. CoRR abs/2402.03640 (2024) - [i25]Ahmed Agiza, Marina Neseem, Sherief Reda:
MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning. CoRR abs/2403.20320 (2024) - [i24]Marina Neseem, Conor McCullough, Randy Hsin, Chas Leichner, Shan Li, In Suk Chong, Andrew G. Howard, Lukasz Lew, Sherief Reda, Ville-Mikko Rautio, Daniele Moro:
PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks. CoRR abs/2404.00103 (2024) - [i23]Ahmed Agiza, Mohamed Mostagir, Sherief Reda:
Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in LLMs. CoRR abs/2404.08699 (2024) - [i22]Manar Abdelatty, Sherief Reda:
HDLCopilot: Hardware Design Library Querying with Natural Language. CoRR abs/2407.12749 (2024) - [i21]Manar Abdelatty, Jingxiao Ma, Sherief Reda:
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs. CoRR abs/2411.03471 (2024) - 2023
- [c101]Jingxiao Ma, Sherief Reda:
RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. ASP-DAC 2023: 140-145 - [c100]Manar Abdelatty, Joseph Incandela, Kangping Hu, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein:
Microscale 3-D Capacitance Tomography with a CMOS Sensor Array. BioCAS 2023: 1-5 - [c99]Marina Neseem, Ahmed Agiza, Sherief Reda:
AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning. CVPR Workshops 2023: 4730-4739 - [c98]Ahmed Agiza, Rajarshi Roy, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro:
GraPhSyM: Graph Physical Synthesis Model. ICCAD 2023: 1-9 - [c97]Jingxiao Ma, Sherief Reda:
WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference. ISLPED 2023: 1-6 - [i20]Marina Neseem, Ahmed Agiza, Sherief Reda:
AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning. CoRR abs/2304.08594 (2023) - [i19]Abdelrahman Hosny, Sherief Reda:
Automatic MILP Solver Configuration By Learning Problem Similarities. CoRR abs/2307.00670 (2023) - [i18]Ahmed Agiza, Rajarshi Roy, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro:
GraPhSyM: Graph Physical Synthesis Model. CoRR abs/2308.03944 (2023) - [i17]Seyed Morteza Nabavinejad, Masoumeh Ebrahimi, Sherief Reda:
Throughput Maximization of DNN Inference: Batching or Multi-Tenancy? CoRR abs/2308.13803 (2023) - [i16]Manar Abdelatty, Joseph Incandela, Kangping Hu, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein:
Microscale 3-D Capacitance Tomography with a CMOS Sensor Array. CoRR abs/2309.09039 (2023) - 2022
- [j38]Yiran Chen, Sherief Reda:
ISLPED 2021: The 25th Anniversary! IEEE Des. Test 39(1): 92-93 (2022) - [j37]Sofiane Chetoui, Sherief Reda:
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices. IEEE Embed. Syst. Lett. 14(1): 3-6 (2022) - [j36]Jingxiao Ma, Soheil Hashemi, Sherief Reda:
Approximate Logic Synthesis Using Boolean Matrix Factorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 15-28 (2022) - [j35]Zihao Yuan, Prachi Shukla, Sofiane Chetoui, Sean S. Nemtzow, Sherief Reda, Ayse K. Coskun:
PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1048-1061 (2022) - [j34]Abdelrahman Hosny, Sherief Reda:
Characterizing and Optimizing EDA Flows for the Cloud. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3040-3051 (2022) - [j33]Seyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi:
Coordinated Batching and DVFS for DNN Inference on GPU Accelerators. IEEE Trans. Parallel Distributed Syst. 33(10): 2496-2508 (2022) - [c96]Sofiane Chetoui, Rahul Shahi, Seif Abdelaziz, Abhinav Golas, Farrukh Hijaz, Sherief Reda:
ARBench: Augmented Reality Benchmark For Mobile Devices. ISPASS 2022: 242-244 - [c95]Sofiane Chetoui, Michael Chen, Abhinav Golas, Farrukh Hijaz, Adel Belouchrani, Sherief Reda:
Alternating Blind Identification of Power Sources for Mobile SoCs. ICPE 2022: 153-164 - [i15]Jingxiao Ma, Sherief Reda:
RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. CoRR abs/2207.00459 (2022) - 2021
- [j32]Seyed Morteza Nabavinejad, Sherief Reda:
BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection. IEEE Comput. Archit. Lett. 20(2): 166-170 (2021) - [j31]Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon:
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test 38(2): 5-7 (2021) - [c94]Seyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi:
BatchSizer: Power-Performance Trade-off for DNN Inference. ASP-DAC 2021: 819-824 - [c93]Abdelrahman Hosny, Sherief Reda:
Characterizing and Optimizing EDA Flows for the Cloud. DATE 2021: 812-815 - [c92]Sofiane Chetoui, Sherief Reda:
Workload- and User-aware Battery Lifetime Management for Mobile SoCs. DATE 2021: 1679-1684 - [c91]Marina Neseem, Sherief Reda:
AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. ICCAD 2021: 1-9 - [c90]Abdelrahman Hosny, Marina Neseem, Sherief Reda:
Sparse Bitmap Compression for Memory-Efficient Training on the Edge. SEC 2021: 14-25 - [i14]Abdelrahman Hosny, Sherief Reda:
Characterizing and Optimizing EDA Flows for the Cloud. CoRR abs/2102.10800 (2021) - [i13]Marina Neseem, Sherief Reda:
AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. CoRR abs/2108.06850 (2021) - [i12]Abdelrahman Hosny, Marina Neseem, Sherief Reda:
BitTrain: Sparse Bitmap Compression for Memory-Efficient Training on the Edge. CoRR abs/2110.15362 (2021) - 2020
- [j30]Krishna Rajan, Soheil Hashemi, Ulya R. Karpuzcu, Michael C. Doggett, Sherief Reda:
Dual-precision fixed-point arithmetic for low-power ray-triangle intersections. Comput. Graph. 87: 72-79 (2020) - [j29]Sofiane Chetoui, Sherief Reda:
Coordinated Self-Tuning Thermal Management Controller for Mobile Devices. IEEE Des. Test 37(5): 34-41 (2020) - [j28]Hokchhay Tann, Heng Zhao, Sherief Reda:
A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks. ACM J. Emerg. Technol. Comput. Syst. 16(1): 8:1-8:23 (2020) - [j27]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda:
Approximate Logic Synthesis: A Survey. Proc. IEEE 108(12): 2195-2213 (2020) - [j26]Reza Azimi, Chao Jing, Sherief Reda:
PowerCoord: Power capping coordination for multi-CPU/GPU servers using reinforcement learning. Sustain. Comput. Informatics Syst. 28: 100412 (2020) - [j25]Fulya Kaplan, Mostafa Said, Sherief Reda, Ayse K. Coskun:
LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 895-908 (2020) - [c89]Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda:
DRiLLS: Deep Reinforcement Learning for Logic Synthesis. ASP-DAC 2020: 581-586 - [c88]Seyed Morteza Nabavinejad, Lena Mashayekhy, Sherief Reda:
ApproxDNN: Incentivizing DNN Approximation in Cloud. CCGRID 2020: 639-648 - [c87]Marina Neseem, Jon Nelson, Sherief Reda:
AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. DAC 2020: 1-6 - [c86]Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Zhengmao Lu, Evelyn Wang, Sherief Reda, Ayse K. Coskun:
A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies. DATE 2020: 400-405 - [c85]Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein:
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring. VLSI-SoC (Selected Papers) 2020: 39-63 - [c84]Xiaoyu Lian, Sherief Reda, Jacob K. Rosenstein:
Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity. VLSI-SOC 2020: 40-45 - [c83]Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein:
Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators. VLSI-SOC 2020: 192-197 - [c82]Sherief Reda:
Overview of the OpenROAD Digital Design Flow from RTL to GDS. VLSI-DAT 2020: 1 - [e4]David Atienza Alonso, Qinru Qiu, Sherief Reda, Yiran Chen:
ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, Massachusetts, August 10-12, 2020. ACM 2020, ISBN 978-1-4503-7053-0 [contents] - [i11]Marina Neseem, Jon Nelson, Sherief Reda:
AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. CoRR abs/2006.05884 (2020)
2010 – 2019
- 2019
- [j24]Seyed Morteza Nabavinejad, Hassan Hafez-Kolahi, Sherief Reda:
Coordinated DVFS and Precision Control for Deep Neural Networks. IEEE Comput. Archit. Lett. 18(2): 136-140 (2019) - [j23]Kumud Nepal, Soheil Hashemi, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Automated High-Level Generation of Low-Power Approximate Computing Circuits. IEEE Trans. Emerg. Top. Comput. 7(1): 18-30 (2019) - [c81]Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu:
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC 2019: 76 - [c80]Soheil Hashemi, Sherief Reda:
Generalized Matrix Factorization Techniques for Approximate Logic Synthesis. DATE 2019: 1289-1292 - [c79]Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Sherief Reda, Evelyn Wang, Ayse K. Coskun:
Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers. ISLPED 2019: 1-6 - [p5]Soheil Hashemi, Sherief Reda:
Approximate Multipliers and Dividers Using Dynamic Bit Selection. Approximate Circuits 2019: 25-44 - [p4]Soheil Hashemi, Hokchhay Tann, Sherief Reda:
Approximate Logic Synthesis Using Boolean Matrix Factorization. Approximate Circuits 2019: 141-154 - [p3]Hokchhay Tann, Soheil Hashemi, Sherief Reda:
Lightweight Deep Neural Network Accelerators Using Approximate SW/HW Techniques. Approximate Circuits 2019: 289-305 - [p2]Hokchhay Tann, Soheil Hashemi, Francesco Buttafuoco, Sherief Reda:
Approximate Computing for Iris Recognition Systems. Approximate Circuits 2019: 331-348 - [e3]Sherief Reda, Muhammad Shafique:
Approximate Circuits, Methodologies and CAD. Springer 2019, ISBN 978-3-319-99321-8 [contents] - [i10]Jacob K. Rosenstein, Christopher Rose, Sherief Reda, Peter M. Weber, Eunsuk Kim, Jason Sello, Joseph Geiser, Eamonn Kennedy, Christopher E. Arcadia, Amanda Dombroski, Kady Oakley, Shui Ling Chen, Hokchhay Tann, Brenda M. Rubenstein:
Principles of Information Storage in Small-Molecule Mixtures. CoRR abs/1905.02187 (2019) - [i9]Hokchhay Tann, Heng Zhao, Sherief Reda:
A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks. CoRR abs/1909.03385 (2019) - [i8]Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda:
DRiLLS: Deep Reinforcement Learning for Logic Synthesis. CoRR abs/1911.04021 (2019) - 2018
- [j22]Reza Azimi, Tyler Fox, Wendy Gonzalez, Sherief Reda:
Scale-Out vs Scale-Up: A Study of ARM-based SoCs on Server-Class Workloads. ACM Trans. Model. Perform. Evaluation Comput. Syst. 3(4): 18:1-18:23 (2018) - [c78]Soheil Hashemi, Hokchhay Tann, Sherief Reda:
BLASYS: approximate logic synthesis using boolean matrix factorization. DAC 2018: 55:1-55:6 - [c77]Seyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi, Sherief Reda:
QoR-aware power capping for approximate big data processing. DATE 2018: 253-256 - [c76]Soheil Hashemi, Hokchhay Tann, Francesco Buttafuoco, Sherief Reda:
Approximate computing for biometrie security systems: A case study on iris scanning. DATE 2018: 319-324 - [c75]Reza Azimi, Chao Jing, Sherief Reda:
PowerCoord: A Coordinated Power Capping Controller for Multi-CPU/GPU Servers. IGSC 2018: 1-9 - [c74]Mostafa Said, Sofiane Chetoui, Adel Belouchrani, Sherief Reda:
Understanding the Sources of Power Consumption in Mobile SoCs. IGSC 2018: 1-7 - [c73]Christopher E. Arcadia, Hokchhay Tann, Amanda Dombroski, Kady Ferguson, Shui Ling Chen, Eunsuk Kim, Christopher Rose, Brenda M. Rubenstein, Sherief Reda, Jacob K. Rosenstein:
Parallelized Linear Classification with Volumetric Chemical Perceptrons. ICRC 2018: 1-9 - [c72]Christopher Rose, Sherief Reda, Brenda M. Rubenstein, Jacob K. Rosenstein:
Computing with Chemicals: Perceptrons Using Mixtures of Small Molecules. ISIT 2018: 2236-2240 - [i7]Hokchhay Tann, Soheil Hashemi, Sherief Reda:
Flexible Deep Neural Network Processing. CoRR abs/1801.07353 (2018) - [i6]Soheil Hashemi, Hokchhay Tann, Sherief Reda:
BLASYS: Approximate Logic Synthesis Using Boolean Matrix Factorization. CoRR abs/1805.06050 (2018) - [i5]Kapil Dev, Indrani Paul, Wei Huang, Yasuko Eckert, Wayne P. Burleson, Sherief Reda:
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques. CoRR abs/1808.09651 (2018) - [i4]Christopher E. Arcadia, Hokchhay Tann, Amanda Dombroski, Kady Ferguson, Shui Ling Chen, Eunsuk Kim, Christopher Rose, Brenda M. Rubenstein, Sherief Reda, Jacob K. Rosenstein:
Parallelized Linear Classification with Volumetric Chemical Perceptrons. CoRR abs/1810.05214 (2018) - 2017
- [j21]Xin Zhan, Reza Azimi, Svilen Kanev, David M. Brooks, Sherief Reda:
CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. IEEE Comput. Archit. Lett. 16(1): 6-9 (2017) - [j20]Kapil Dev, Xin Zhan, Sherief Reda:
Scheduling on CPU + GPU Processors Under Dynamic Conditions. J. Low Power Electron. 13(4): 551-568 (2017) - [c71]Reza Azimi, Tyler Fox, Sherief Reda:
Understanding the Role of GPGPU-Accelerated SoC-Based ARM Clusters. CLUSTER 2017: 333-343 - [c70]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. DAC 2017: 28:1-28:6 - [c69]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the impact of precision quantization on the accuracy and energy of neural networks. DATE 2017: 1474-1479 - [c68]Sherief Reda, Adel Belouchrani:
Blind identification of power sources in processors. DATE 2017: 1739-1744 - [c67]Reza Azimi, Masoud Badiei, Xin Zhan, Na Li, Sherief Reda:
Fast Decentralized Power Capping for Server Clusters. HPCA 2017: 181-192 - [c66]Samuel Steffl, Sherief Reda:
LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs. ICCD 2017: 137-144 - [c65]Mohamed Shalan, Sherief Reda:
CloudV: A cloud-based educational digital design environment. MSE 2017: 39-42 - [i3]Hokchhay Tann, Soheil Hashemi, Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. CoRR abs/1705.04288 (2017) - 2016
- [c64]Masoud Badiei, Xin Zhan, Reza Azimi, Sherief Reda, Na Li:
DiBA: Distributed Power Budget Allocation for Large-Scale Computing Clusters. CCGrid 2016: 70-79 - [c63]Xin Zhan, Mohammed Shoaib, Sherief Reda:
Creating Soft Heterogeneity in Clusters Through Firmware Re-configuration. CCGrid 2016: 540-549 - [c62]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime configurable deep neural networks for energy-accuracy trade-off. CODES+ISSS 2016: 34:1-34:10 - [c61]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
A low-power dynamic divider for approximate applications. DAC 2016: 105:1-105:6 - [c60]Kapil Dev, Sherief Reda:
Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors. ESTIMedia 2016: 78-83 - [c59]Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar:
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. FPL 2016: 1-9 - [c58]Kapil Dev, Xin Zhan, Sherief Reda:
Power-aware characterization and mapping of workloads on CPU-GPU processors. IISWC 2016: 225-226 - [c57]Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne P. Burleson:
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. ISVLSI 2016: 242-247 - [i2]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. CoRR abs/1607.05418 (2016) - [i1]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. CoRR abs/1612.03940 (2016) - 2015
- [j19]Xin Zhan, Sherief Reda:
Power Budgeting Techniques for Data Centers. IEEE Trans. Computers 64(8): 2267-2278 (2015) - [c56]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. ICCAD 2015: 418-425 - [c55]Reza Azimi, Xin Zhan, Sherief Reda:
How Good Are Low-Power 64-Bit SoCs for Server-Class Workloads? IISWC 2015: 116-117 - [c54]Sriram Jayakumar, Sherief Reda:
Making sense of thermoelectrics for processor thermal management and energy harvesting. ISLPED 2015: 31-36 - 2014
- [j18]Abdullah Nazma Nowroz, Kangqiao Hu, Farinaz Koushanfar, Sherief Reda:
Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1792-1805 (2014) - [j17]Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda:
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. ACM Trans. Reconfigurable Technol. Syst. 7(1): 4:1-4:22 (2014) - [c53]Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda:
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. DATE 2014: 1-6 - [c52]Reza Azimi, Xin Zhan, Sherief Reda:
Thermal-aware layout planning for heterogeneous datacenters. ISLPED 2014: 245-250 - 2013
- [j16]Sherief Reda, Abdullah Nazma Nowroz, Ryan Cochran, Stefan Angelevski:
Post-silicon power mapping techniques for integrated circuits. Integr. 46(1): 69-79 (2013) - [j15]Abdullah Nazma Nowroz, Gary L. Woods, Sherief Reda:
Power Mapping of Integrated Circuits Using AC-Based Thermography. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1398-1409 (2013) - [c51]Kapil Dev, Gary L. Woods, Sherief Reda:
High-throughput TSV testing and characterization for 3D integration using thermal mapping. DAC 2013: 73:1-73:6 - [c50]Xin Zhan, Sherief Reda:
Techniques for energy-efficient power budgeting in data centers. DAC 2013: 176:1-176:7 - [c49]Kangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda, Farinaz Koushanfar:
High-sensitivity hardware trojan detection using multimodal characterization. DATE 2013: 1271-1276 - [c48]Francesco Paterna, Sherief Reda:
Mitigating dark-silicon problems using superlattice-based thermoelectric coolers. DATE 2013: 1391-1394 - [c47]Kapil Dev, Abdullah Nazma Nowroz, Sherief Reda:
Power mapping and modeling of multi-core processors. ISLPED 2013: 39-44 - [c46]Can Hankendi, Sherief Reda, Ayse K. Coskun:
vCap: Adaptive power capping for virtualized servers. ISLPED 2013: 415-420 - 2012
- [j14]Sherief Reda, Abdullah Nazma Nowroz:
Power Modeling and Characterization of Computing Devices: A Survey. Found. Trends Electron. Des. Autom. 6(2): 121-216 (2012) - [j13]Sherief Reda, Ryan Cochran, Ayse K. Coskun:
Adaptive Power Capping for Servers with Multithreaded Workloads. IEEE Micro 32(5): 64-75 (2012) - [j12]Ryan Cochran, Sherief Reda:
Thermal prediction and adaptive control through workload phase detection. ACM Trans. Design Autom. Electr. Syst. 18(1): 7:1-7:19 (2012) - [c45]Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda:
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM 2012: 65-68 - [c44]Dhireesha Kudithipudi, Ayse K. Coskun, Sherief Reda, Qinru Qiu:
Temperature-aware computing: Achievements and remaining challenges. IGCC 2012: 1-3 - 2011
- [j11]Sherief Reda:
Thermal and Power Characterization of Real Computing Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 76-87 (2011) - [j10]Sherief Reda, Ryan Cochran, Abdullah Nazma Nowroz:
Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques. IEEE Trans. Computers 60(6): 841-851 (2011) - [c43]Abdullah Nazma Nowroz, Gary L. Woods, Sherief Reda:
Improved post-silicon power modeling using AC lock-in techniques. DAC 2011: 101-106 - [c42]Abdullah Nazma Nowroz, Sherief Reda:
Thermal and power characterization of field-programmable gate arrays. FPGA 2011: 111-114 - [c41]Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda:
Identifying the optimal energy-efficient operating points of parallel workloads. ICCAD 2011: 608-615 - [c40]Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda:
Pack & Cap: adaptive DVFS and thread packing under power caps. MICRO 2011: 175-185 - 2010
- [c39]Nauman H. Khan, Sherief Reda, Soha Hassoun:
Early estimation of TSV area for power delivery in 3-D integrated circuits. 3DIC 2010: 1-6 - [c38]Abdullah Nazma Nowroz, Ryan Cochran, Sherief Reda:
Thermal monitoring of real processors: techniques for sensor allocation and full characterization. DAC 2010: 56-61 - [c37]Ryan Cochran, Sherief Reda:
Consistent runtime thermal prediction and control through workload phase detection. DAC 2010: 62-67 - [c36]Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda:
Post-silicon power characterization using thermal infrared emissions. ISLPED 2010: 331-336 - [c35]Jinhai Qiu, Sherief Reda, Soha Hassoun:
Fast, accurate a priori routing delay estimation. SLIP 2010: 77-82 - [e2]Sherief Reda, Janet Meiling Wang:
International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010. ACM 2010, ISBN 978-1-4503-0037-7 [contents]
2000 – 2009
- 2009
- [j9]Sherief Reda, Gregory Smith, Larry Smith:
Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1357-1362 (2009) - [c34]Ryan Cochran, Sherief Reda:
Spectral techniques for high-resolution thermal characterization with limited sensor data. DAC 2009: 478-483 - [c33]Sherief Reda, Sani R. Nassif:
Analyzing the impact of process variations on parametric measurements: Novel models and applications. DATE 2009: 375-380 - [c32]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286 - [c31]Michael Kadin, Sherief Reda, Augustus K. Uht:
Central vs. distributed dynamic thermal management for multi-core processors: which one is better? ACM Great Lakes Symposium on VLSI 2009: 137-140 - [c30]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256 - [c29]Sherief Reda, Aung Si, R. Iris Bahar:
Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286 - [c28]Sherief Reda:
Using circuit structural analysis techniques for networks in systems biology. SLIP 2009: 37-44 - [e1]Chung-Kuan Cheng, Sherief Reda:
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings. ACM 2009, ISBN 978-1-60558-576-5 [contents] - 2008
- [j8]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Parametric yield management for 3D ICs: Models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. 4(4): 19:1-19:22 (2008) - [c27]Brendan Hargreaves, Henrik Hult, Sherief Reda:
Within-die process variations: How accurately can they be statistically modeled? ASP-DAC 2008: 524-530 - [c26]Michael Kadin, Sherief Reda:
Frequency and voltage planning for multi-core processors under thermal constraints. ICCD 2008: 463-470 - [c25]Michael Kadin, Sherief Reda:
Frequency planning for multi-core processors under thermal constraints. ISLPED 2008: 213-216 - 2007
- [c24]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226 - [c23]David Meisner, Sherief Reda:
Hardware libraries: An architecture for economic acceleration in soft multi-core environments. ICCD 2007: 179-186 - [c22]Andrew B. Kahng, Sherief Reda, Puneet Sharma:
On-Line Adjustable Buffering for Runtime Power Reduction. ISQED 2007: 550-555 - [p1]Andrew B. Kahng, Sherief Reda, Qinke Wang:
APlace: A High Quality, Large-Scale Analytical Placer. Modern Circuit Placement 2007: 167-192 - 2006
- [j7]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2): 305-320 (2006) - [j6]Andrew B. Kahng, Sherief Reda:
New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 533-543 (2006) - [j5]Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 678-691 (2006) - [j4]Andrew B. Kahng, Sherief Reda:
Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1301-1312 (2006) - [j3]Andrew B. Kahng, Sherief Reda:
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2806-2819 (2006) - [c21]Sherief Reda, Amit Chowdhary:
Effective linear programming based placement methods. ISPD 2006: 186-191 - [c20]Andrew B. Kahng, Sherief Reda:
A tale of two nets: studies of wirelength progression in physical design. SLIP 2006: 17-24 - 2005
- [c19]Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang:
Power-aware placement. DAC 2005: 795-800 - [c18]Andrew B. Kahng, Sherief Reda:
Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD 2005: 173-180 - [c17]Andrew B. Kahng, Sherief Reda, Qinke Wang:
Architecture and details of a high quality, large-scale analytical placer. ICCAD 2005: 891-898 - [c16]Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 - [c15]Andrew B. Kahng, Sherief Reda:
Evaluation of placer suboptimality via zero-change netlist transformations. ISPD 2005: 208-215 - [c14]Andrew B. Kahng, Sherief Reda, Qinke Wang:
APlace: a general analytic placement framework. ISPD 2005: 233-235 - 2004
- [j2]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Scalable Heuristics for Design of DNA Probe Arrays. J. Comput. Biol. 11(2/3): 429-447 (2004) - [j1]Andrew B. Kahng, Sherief Reda:
Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. 32(6): 499-509 (2004) - [c13]Andrew B. Kahng, Sherief Reda:
Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC 2004: 113-116 - [c12]Andrew B. Kahng, Sherief Reda:
Placement feedback: a concept and method for better min-cut placements. DAC 2004: 357-362 - [c11]Andrew B. Kahng, Igor L. Markov, Sherief Reda:
Boosting: Min-Cut Placement with Improved Signal Delay. DATE 2004: 1098-1103 - [c10]Andrew B. Kahng, Igor L. Markov, Sherief Reda:
On legalization of row-based placements. ACM Great Lakes Symposium on VLSI 2004: 214-219 - 2003
- [c9]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD 2003: 262-269 - [c8]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Design Flow Enhancements for DNA Arrays. ICCD 2003: 116- - [c7]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Engineering a scalable placement heuristic for DNA probe arrays. RECOMB 2003: 148-156 - 2002
- [c6]Sherief Reda, Alex Orailoglu:
Reducing Test Application Time Through Test Data Mutation Encoding. DATE 2002: 387-393 - [c5]Sherief Reda, Rolf Drechsler, Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399 - [c4]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Border Length Minimization in DNA Array Design. WABI 2002: 435-448 - 2001
- [c3]Sherief Reda, Ashraf Salem:
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. DATE 2001: 122-126 - [c2]Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy:
On the use of don't cares during symbolic reachability analysis. ISCAS (5) 2001: 121-124 - 2000
- [c1]Sherief Reda, Ayman Wahba, Ashraf Salem:
M-CHECK: a multiple engine combinational equivalence checker. ISCAS 2000: 613-616
Coauthor Index
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