• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 46 matches

• 2006
• 
  Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
  Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6
• 
  Dmitry Akselrod, Asaf Ashkenazi, Yossi Amon:
  Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs. DATE Designers' Forum 2006: 30-35
• 
  Sutjipto Arifin, Peter Y. K. Cheung:
  A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum 2006: 227-232
• 
  Nico Bannow, Karsten Haug, Wolfgang Rosenstiel:
  Automatic systemC design configuration for a faster evaluation of different partitioning alternatives. DATE Designers' Forum 2006: 217-218
• 
  Federico Baronti, Paolo D'Abramo, Martin Knaipp, Rainer Minixhofer, Roberto Roncella, Roberto Saletti, Martin Schrems, Riccardo Serventi, Verena Vescoli:
  FlexRay transceiver in a 0.35 µm CMOS high-voltage technology. DATE Designers' Forum 2006: 201-205
• 
  Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, Luigi Sportiello:
  Software implementation of Tate pairing over GF(2^m). DATE Designers' Forum 2006: 7-11
• 
  Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari:
  A mixed-signal verification kit for verification of analogue-digital circuits. DATE Designers' Forum 2006: 88-93
• 
  Luciano Bononi, Nicola Concer:
  Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. DATE Designers' Forum 2006: 154-159
• 
  Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano:
  GALS networks on chip: a new solution for asynchronous delay-insensitive links. DATE Designers' Forum 2006: 160-165
• 
  Fabiano Costa Carvalho, Carlos Eduardo Pereira, Elias Teodoro Silva Jr., Edison Pignaton de Freitas:
  A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN. DATE Designers' Forum 2006: 189-194
• 
  Kuo-Hsing Cheng, Yu-Lung Lo:
  A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum 2006: 178-182
• 
  Pierluigi Daglio:
  A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories. DATE Designers' Forum 2006: 94-99
• 
  Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti:
  Synthesis of system verilog assertions. DATE Designers' Forum 2006: 70-75
• 
  Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sánchez-Élez, Nader Bagherzadeh, Fredy Rivera:
  Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). DATE Designers' Forum 2006: 52-57
• 
  John Dielissen, Andries Hekstra, Vincent Berg:
  Low cost LDPC decoder for DVB-S2. DATE Designers' Forum 2006: 130-135
• 
  Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya:
  Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum 2006: 166-171
• 
  Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
  ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238
• 
  Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla:
  Modeling and simulation of mobile gateways interacting with wireless sensor networks. DATE Designers' Forum 2006: 106-111
• 
  Ali Habibi, Haja Moinudeen, Sofiène Tahar:
  Generating finite state machines from SystemC. DATE Designers' Forum 2006: 76-81
• 
  Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo:
  A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69
• 
  Daniele Lo Iacono, J. Zory, Ettore Messina, Nicolo Piazzese, G. Saia, A. Bettinelli:
  ASIP architecture for multi-standard wireless terminals. DATE Designers' Forum 2006: 118-123
• 
  Götz Kappen, Tobias G. Noll:
  Application specific instruction processor based implementation of a GNSS receiver on an FPGA. DATE Designers' Forum 2006: 58-63
• 
  Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia:
  Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226
• 
  Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark A. Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud:
  Industrially proving the SPIRIT consortium specifications for design chain integration. DATE Designers' Forum 2006: 142-147
• 
  Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
  Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17
• 
  Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
  The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum 2006: 244-248
• 
  Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante:
  A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51
• 
  Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek:
  Energy-efficient FPGA interconnect design. DATE Designers' Forum 2006: 42-47
• 
  Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer:
  STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177
• 
  Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello:
  Software-friendly HW/SW co-simulation: an industrial case study. DATE Designers' Forum 2006: 100-105

skipping 16 more matches