IEEE Design & Test of Computers, Volume 18

Volume 18, Number 1, January/February 2001

From the EIC

• 
  D&T and the Future. IEEE Des. Test Comput. 18(1): 1- (2001)

News

• 
  News. IEEE Des. Test Comput. 18(1): 5-7 (2001)

Feature

• 
  Fabrizio Lombardi, Cecilia Metra:
  Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems. IEEE Des. Test Comput. 18(1): 8-9 (2001)
• 
  Jien-Chung Lo, William D. Armitage, Corbet S. Johnson:
  Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. 10-18
• 
  Srikanth Venkataraman, Scott Brady Drummonds:
  Poirot: Applications of a Logic Fault Diagnosis Tool. 19-30
• 
  Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang:
  Defect-Oriented Testing and Defective-Part-Level Prediction. 31-41
• 
  Khurram Muhammad, Kaushik Roy:
  Fault Detection and Location Using IDD Waveform Analysis. 42-49
• 
  Jim Plusquellic:
  IC Diagnosis Using Multiple Supply Pad IDDQs. 50-61

Special Feature

• 
  David San Segundo Bello, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
  Modeling a Verification Test System for Mixed-Signal Circuits. 63-71
• 
  Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg:
  Hierarchical ATPG for Analog Circuits and Systems. 72-81
• 
  A D&T Roundtable: Are Single-Chip Multiprocessors in Reach? IEEE Des. Test Comput. 18(1): 82-89 (2001)

Panel Summaries

• 
  Panel Summaries. IEEE Des. Test Comput. 18(1): 90-92 (2001)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 18(1): 93- (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(1): 94- (2001)

TTTC Newsletter

• 
  TTTC Newsletter. IEEE Des. Test Comput. 18(1): 95- (2001)

The Last Byte

• 
  Danger! Submicron Defects! IEEE Des. Test Comput. 18(1): 96- (2001)

Volume 18, Number 2, March/April 2001

EIC Message

• 
  Managing Power. IEEE Des. Test Comput. 18(2): 1- (2001)

Feature

• 
  Enrico Macii:
  Guest Editor's Introduction: Dynamic Power Management of Electronic Systems. IEEE Des. Test Comput. 18(2): 6-9 (2001)
• 
  Yung-Hsiang Lu, Giovanni De Micheli:
  Comparing System-Level Power Management Policies. 10-19
• 
  Dongkun Shin, Jihong Kim, Seongsoo Lee:
  Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications. 20-30
• 
  Takanori Okuma, Hiroto Yasuura, Tohru Ishihara:
  Software Energy Reduction Techniques for Variable-Voltage Processors. 31-41
• 
  Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple:
  Power Management in the Amulet Microprocessors. 42-52
• 
  Luca Benini, Giuliano Castelli, Alberto Macii, Riccardo Scarsi:
  Battery-Driven Dynamic Power Management. 53-60
• 
  Amit Sinha, Anantha P. Chandrakasan:
  Dynamic Power Management in Wireless Sensor Networks. 62-74

Special Feature

• 
  Manoj Sachdev:
  Current-Based Testing for Deep-Submicron VLSIs. 76-84

Panel Summaries

• 
  Panel Summaries. IEEE Des. Test Comput. 18(2): 86-91 (2001)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 18(2): 92-94 (2001)

Standards

• 
  Standards. IEEE Des. Test Comput. 18(2): 95- (2001)

Special Feature

• 
  A D&T Roundtable: Industrial and University Test Research Collaboration. IEEE Des. Test Comput. 18(2): 98-105 (2001)

TTTC Newsletter

• 
  TTTC Newsletter. IEEE Des. Test Comput. 18(2): 109-110 (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(2): 111- (2001)

The Last Byte

• 
  Scott Davidson:
  Welcome to 2001. IEEE Des. Test Comput. 18(2): 112- (2001)

Volume 18, Number 3, May/June 2001

From the EIC

• 
  Yervant Zorian:
  Huge Storage Capacity. IEEE Des. Test Comput. 18(3): 1- (2001)

Feature

• 
  Rochit Rajsuman, Francky Catthoor:
  Guest Editors' Intoduction: The New World of Large Embedded Memories. IEEE Des. Test Comput. 18(3): 3-4 (2001)

Perspectives

• 
  Alex Shubat:
  Moving the Market to Embedded Memory. IEEE Des. Test Comput. 18(3): 5-6 (2001)

Feature

• 
  Doris Keitel-Schulz, Norbert Wehn:
  Embedded DRAM Development: Technology, Physical Design, and Application Issues. 7-15
• 
  Rochit Rajsuman:
  Design and Test of Large Embedded Memories: An Overview. 16-27
• 
  Julie Segal, Alvin Jee, David Y. Lepejian, Ben Chu:
  Using Electrical Bitmap Results from Embedded Memory to Enhance Yield. 28-39
• 
  Lode Nachtergaele, Francky Catthoor, Chidamber Kulkarni:
  Random-Access Data Storage Components in Customized Architectures. 40-54
• 
  Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef:
  Data Memory Organization and Optimizations in Application-Specific Systems. 56-68
• 
  Francky Catthoor, Koen Danckaert, Sven Wuytack, Nikil D. Dutt:
  Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors. 70-82

Special Feature

• 
  Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane:
  System-on-Chip Testability Using LSSD Scan Structures. 83-97
• 
  Margarida F. Jacome, Helvio P. Peixoto:
  A Survey of Digital Design Reuse. 98-107
• 
  Michael Sprachmann:
  Automatic Generation of Parallel CRC Circuits. 108-114

Roundtable

• 
  A D&T Roundtable: System-on-Chip Specification and Modeling Using C++: Challenges and Opportunities. IEEE Des. Test Comput. 18(3): 115-123 (2001)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 18(3): 124-126 (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(3): 127- (2001)

The Last Byte

• 
  Ahmed Amine Jerraya:
  Two Enduring Questions for Computer Design. IEEE Des. Test Comput. 18(3): 128- (2001)

Volume 18, Number 4, July/August 2001

EIC Message

• 
  Yervant Zorian:
  Error-Free Products. IEEE Des. Test Comput. 18(4): 2- (2001)

Features

• 
  Carl Pixley:
  Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Des. Test Comput. 18(4): 4-5 (2001)
• 
  Harry Foster:
  Applied Boolean Equivalence Verification and RTL Static Sign-Off. 6-15
• 
  Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham:
  Practical Formal Verification in Microprocessor Design. 16-25
• 
  Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham:
  Design and Development Paradigm for Industrial Formal Verification CAD Tools. 26-35
• 
  Serdar Tasiran, Kurt Keutzer:
  Coverage Metrics for Functional Validation of Hardware Designs. 36-45

Special Feature

• 
  Lionel Bening, Harry Foster:
  Optimizing Multiple EDA Tools within the ASIC Design Flow. 46-55
• 
  Roberto d'Amore, Osamu Saotome, Karl Heinz Kienitz:
  A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors. 56-64

Roundtable

• 
  Roundtable: Adding Reconfigurable Logic to SOC Designs. IEEE Des. Test Comput. 18(4): 65-71 (2001)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 18(4): 72- (2001)

Panel Summaries

• 
  Panel Summaries. IEEE Des. Test Comput. 18(4): 73-76 (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(4): 77- (2001)

TTCC Newsletter

• 
  TTCC Newsletter. IEEE Des. Test Comput. 18(4): 78-79 (2001)

The Last Byte

• 
  Todd M. Austin:
  Design for Verification? IEEE Des. Test Comput. 18(4): 80, 77 (2001)

Volume 18, Number 5, September/October 2001

From the EIC

• 
  Yervant Zorian:
  EIC Message. IEEE Des. Test Comput. 18(5): 1- (2001)

News

• 
  News. IEEE Des. Test Comput. 18(5): 5-6 (2001)

Feature

• 
  Wayne H. Wolf, Ahmed Amine Jerraya:
  Application-Specific System-on-a-Chip Multiprocessors. IEEE Des. Test Comput. 18(5): 7- (2001)
• 
  Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya:
  Colif: A Design Representation for Application-Specific Multiprocessor SOCs. 8-20
• 
  Santanu Dutta, Rune Jensen, Alf Rieckmann:
  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. 21-31
• 
  Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau:
  Automating the Design of SOCs Using Cores. 32-45
• 
  Peng Yang, Chun Wong, Paul Marchal, Francky Catthoor, Dirk Desmet, Diederik Verkest, Rudy Lauwereins:
  Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs. 46-58
• 
  Tony Ambler, Donald L. Wheater:
  Test Trade-Offs Take Center Stage at ITC. IEEE Des. Test Comput. 18(5): 59- (2001)
• 
  Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir:
  Very Low Cost Testers: Opportunities and Challenges. 60-69
• 
  Louis Y. Ungar, Tony Ambler:
  Economics of Built-in Self-Test. 70-79
• 
  Anshuman Chandra, Krishnendu Chakrabarty:
  Test Resource Partitioning for SOCs. 80-91
• 
  Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni:
  Online and Offline BIST in IP-Core Design. 92-99

Special Feature

• 
  Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi:
  Making Java Work for Microcontroller Applications. 100-110

Roundtable

• 
  Design Closure with Cell-Based Synthesis. IEEE Des. Test Comput. 18(5): 112-119 (2001)

Conference Reports

• 
  Technology Continuous Education. IEEE Des. Test Comput. 18(5): 120- (2001)

Panel Summaries

• 
  Tom Anderson:
  Your Core-My Problem? Integration and Verification of IP. IEEE Des. Test Comput. 18(5): 121, 123 (2001)

Standards

• 
  Peter J. Ashenden:
  VHDL Standards. IEEE Des. Test Comput. 18(5): 122-123 (2001)

New Products

• 
  New Products. IEEE Des. Test Comput. 18(5): 124- (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(5): 125- (2001)

TTTC Newsletter

• 
  TTTC Newsletter. IEEE Des. Test Comput. 18(5): 126-127 (2001)

The Last Byte

• 
  Tony Ambler:
  Test Strategies and Marriage Partners. IEEE Des. Test Comput. 18(5): 128- (2001)

Volume 18, Number 6, November/December 2001

EIC Message

• 
  EIC Message. IEEE Des. Test Comput. 18(6): 3- (2001)

Features

• 
  William H. Joyner Jr., Andrew B. Kahng:
  Guest Editor's Introduction: Roadmaps and Visions for Design and Test. IEEE Des. Test Comput. 18(6): 4-5 (2001)
• 
  Dennis Sylvester, Himanshu Kaul:
  Power-Driven Challenges in Nanometer Design. 12-22
• 
  Alberto L. Sangiovanni-Vincentelli, Grant Martin:
  Platform-Based Design and Software Design Methodology for Embedded Systems. 23-33
• 
  Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt:
  A Mixed-Signal Design Roadmap. 34-46
• 
  Rohit Kapur, R. Chandramouli, Thomas W. Williams:
  Strategies for Low-Cost Test. 47-54

Special Feature

• 
  Kevin Stanley:
  High-Accuracy Flush-and-Scan Software Diagnostic. 56-62

Perspectives

• 
  Perspectives. IEEE Des. Test Comput. 18(6): 6-11 (2001)

Conference Reports

• 
  Conference Reports. IEEE Des. Test Comput. 18(6): 64-65 (2001)

Panel Summaries

• 
  Panel Summaries. IEEE Des. Test Comput. 18(6): 66-67 (2001)

TTTC Newsletter

• 
  TTTC Newsletter. IEEE Des. Test Comput. 18(6): 68- (2001)

DATC Newsletter

• 
  DATC Newsletter. IEEE Des. Test Comput. 18(6): 69- (2001)

Annual Index

• 
  Annual Index. IEEE Des. Test Comput. 18(6): 70-79 (2001)

The Last Byte

• 
  The Last Byte. IEEE Des. Test Comput. 18(6): 80- (2001)