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2020 – today
- 2024
[j35]Tomohiro Nishiguchi, Nobutaka Kuroki, Masahiro Numa:
Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 592-599 (2024)- 2021
- [j34]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. IEICE Electron. Express 18(6): 20210065 (2021) - [j33]Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa:
Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning. IEICE Trans. Inf. Syst. 104-D(1): 183-193 (2021) - 2020
- [j32]Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. IEICE Electron. Express 17(11): 20200103 (2020) - [j31]Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa:
Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(7): 955-958 (2020) - [c34]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. NEWCAS 2020: 38-41 - [c33]Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa:
Detecting tampered regions in JPEG images via CNN. NEWCAS 2020: 202-205
2010 – 2019
- 2019
- [c32]Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. ICECS 2019: 530-533 - 2018
- [j30]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems. IEICE Trans. Electron. 101-C(3): 161-169 (2018) - [c31]Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices. ICECS 2018: 209-212 - [c30]Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. ISCAS 2018: 1-5 - [c29]Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. VLSI-SoC 2018: 196-200 - 2017
- [j29]Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Multi-Channel Convolutional Neural Networks for Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 572-580 (2017) - [j28]Ryo Matsuzuka, Tetsuya Hirose
, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa:
An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2026-2035 (2017) - [c28]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. ASP-DAC 2017: 35-36 - [c27]Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting. ICECS 2017: 498-501 - [c26]Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting. ICECS 2017: 502-505 - [c25]Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications. ISCAS 2017: 1-4 - 2016
- [j27]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2491-2499 (2016) - [j26]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting. IEEE J. Solid State Circuits 51(10): 2398-2407 (2016) - [c24]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management. A-SSCC 2016: 225-228 - [c23]Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability. ESSCIRC 2016: 149-152 - [c22]Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa:
A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems. NEWCAS 2016: 1-4 - [c21]Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Image super-resolution with multi-channel convolutional neural networks. NEWCAS 2016: 1-4 - 2015
- [j25]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express 12(4): 20141157 (2015) - [j24]Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs. IEICE Trans. Electron. 98-C(5): 446-453 (2015) - [j23]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2600-2606 (2015) - [c20]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. ASP-DAC 2015: 30-31 - [c19]Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa:
A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting. A-SSCC 2015: 1-4 - [c18]Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa:
A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. ISCAS 2015: 2948-2951 - 2014
- [j22]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit. IEICE Trans. Electron. 97-C(6): 512-518 (2014) - [c17]Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters. ESSCIRC 2014: 255-258 - [c16]Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada:
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS 2014: 137-140 - 2013
- [j21]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE J. Solid State Circuits 48(6): 1530-1538 (2013) - [c15]Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application. ESSCIRC 2013: 315-318 - 2012
- [j20]Masahiro Numa:
FOREWORD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2171 (2012) - [j19]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits 47(7): 1776-1783 (2012) - [c14]Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi:
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC 2012: 69-72 - [c13]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. ICECS 2012: 97-100 - [c12]Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A low-power single-slope analog-to-digital converter with digital PVT calibration. ICECS 2012: 613-616 - 2011
- [j18]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs. IEICE Electron. Express 8(12): 890-896 (2011) - [j17]Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa:
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Trans. Electron. 94-C(1): 80-88 (2011) - [j16]Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Trans. Electron. 94-C(6): 1042-1048 (2011) - [c11]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC 2011: 113-114 - [c10]Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 18.9-nA standby current comparator with adaptive bias current generator. A-SSCC 2011: 237-240 - [c9]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202 - 2010
- [j15]Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
An Error Diagnosis Technique Based on Clustering of Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2490-2496 (2010) - [c8]Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. ESSCIRC 2010: 114-117 - [c7]Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa:
Super-resolution technique for thermography with dual-camera system. ISCAS 2010: 1895-1898
2000 – 2009
- 2009
- [j14]Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi:
A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control. IEICE Electron. Express 6(8): 456-460 (2009) - [j13]Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3136-3142 (2009) - 2008
- [j12]Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa:
Delayed-ABC SOI for crosstalk noise repair. IEICE Electron. Express 5(9): 354-360 (2008) - [j11]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. J. Comput. 3(5): 34-40 (2008) - 2007
- [j10]Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa:
Charge recycling in MTCMOS circuits with block dividing. IEICE Electron. Express 4(18): 562-568 (2007) - [j9]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa:
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Trans. Electron. 90-C(4): 666-674 (2007) - [j8]Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2691-2694 (2007) - [c6]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. VLSI Design 2007: 609-614 - 2006
- [j7]Akira Tada, Hiromi Notani, Masahiro Numa:
A novel power gating scheme with charge recycling. IEICE Electron. Express 3(12): 281-286 (2006) - [j6]Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI. IEICE Electron. Express 3(21): 453-458 (2006) - [j5]Nobutaka Kuroki, Nobuhiro Oka, Masahiro Numa, Keisuke Yamamoto:
An Evaluation of Triple Density Error Diffusion for Medical Monochrome LCDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1866-1868 (2006) - [c5]Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa:
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. PATMOS 2006: 393-402 - 2004
- [c4]Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata:
A technique for high-speed circuits on SOI using look-ahead type active body bias control. ISCAS (2) 2004: 405-408 - [c3]Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada:
Leakage power reduction for clock gating scheme on PD-SOI. ISCAS (2) 2004: 613-616 - [c2]Nobutaka Kuroki, Takahiro Manabe, Masahiro Numa:
Adaptive arithmetic coding for image prediction errors. ISCAS (3) 2004: 961-964 - [c1]Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada:
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. PATMOS 2004: 423-432 - 2003
- [j4]Hiroshi Inoue, Takahiro Iwasaki, Toshifumi Sugane, Masahiro Numa, Keisuke Yamamoto:
Application of Error Diagnosis Technique to Incremental Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3214-3217 (2003) - 2000
- [j3]Hirokazu Masuda, Nobutaka Kuroki, Masahiro Numa, Kotaro Hirano:
Layered blind deconvolution with interband prediction. Syst. Comput. Jpn. 31(3): 77-83 (2000)
1990 – 1999
- 1997
- [j2]Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita:
A diagnosis method for single logic design errors in gate-level combinational circuits. Syst. Comput. Jpn. 28(6): 30-39 (1997) - 1995
- [j1]Changzheng Wang, Masahiro Numa, Kotaro Hirano:
ATM data transmission systems based on N-ISDN. IEEE Trans. Commun. 43(2/3/4): 1785-1792 (1995)
Coauthor Index
[j35] [j34] [j33] [j32] [j31] [c34] [c33] [c32] [j30] [c31] [c30] [c29] [j29] [j28] [c28] [c27] [c26] [c25] [j27] [j26] [c24] [c23] [c22] [c21] [j25] [j24] [j23] [c20] [c19] [c18] [j22] [c17] [c16] [j21] [c15] [j19] [c14] [c13] [c12] [j18] [j17] [j16] [c11] [c10] [c9] [j15] [c8] [c7] [j13] [j5] [c2] [j3]
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