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ORCIDStephen Y. H. Su
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1990 – 1999
- 1997
[c24]Stephen Y. H. Su, Rong Yao:
Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays. PDPTA 1997: 1633-1642- 1991
- [j27]Stephen Y. H. Su, Michal Cutler, Mingshien Wang:
Self-Diagnosis of Faelures in VLSI Tree Array Processors. IEEE Trans. Computers 40(11): 1252-1257 (1991) - [c23]Michal Cutler, Stephen Y. H. Su, Mingshien Wang:
Distributed self-diagnosis of VLSI mesh array processors. VTS 1991: 178-186
1980 – 1989
- 1989
- [j26]Mingshien Wang, Michal Cutler, Stephen Y. H. Su:
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy. IEEE Trans. Computers 38(4): 547-554 (1989) - 1988
- [j25]Li Shen, Stephen Y. H. Su:
A Functional Testing Method for Microprocessors. IEEE Trans. Computers 37(10): 1288-1293 (1988) - [c22]Stephen Y. H. Su, Hede Ma:
Fault Isolation in Grey Systems. ITC 1988: 54-63 - [c21]Stephen Y. H. Su, Hede Ma:
Designs for Diagnosability and Reliability in VLSI Systems. ITC 1988: 888-897 - 1986
- [j24]Israel Koren, Zahava Koren, Stephen Y. H. Su:
Analysis of a Class of Recovery Procedures. IEEE Trans. Computers 35(8): 703-712 (1986) - 1985
- [j23]Shiyi Xu, Stephen Y. H. Su:
Detecting I/O and Internal Feedback Bridging Faults. IEEE Trans. Computers 34(6): 553-557 (1985) - [j22]Tonysheng Lin, Stephen Y. H. Su:
The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 250-263 (1985) - [c20]Tonysheng Lin, Stephen Y. H. Su:
VLSI Functional Test Pattern Generation: A Design and Implementation. ITC 1985: 922-929 - 1984
- [c19]Stephen Y. H. Su:
IDAS: an integrated design automation system. AFIPS National Computer Conference 1984: 143-150 - [c18]Stephen Y. H. Su, Tonysheng Lin:
Functional testing techniques for digital LSI/VLSI systems. DAC 1984: 517-528 - [c17]Li Shen, Stephen Y. H. Su:
VLSI functional testing using critical path traces at hardware description language level. Fehlertolerierende Rechensysteme 1984: 364-379 - [c16]Tonysheng Lin, Stephen Y. H. Su:
Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. ITC 1984: 660-668 - 1983
- [c15]Kewal K. Saluja, Li Shen, Stephen Y. H. Su:
A Simplified Algorithm for Testing Microprocessors. ITC 1983: 668-675 - 1982
- [j21]Yacoub M. El-Ziq, Stephen Y. H. Su:
Fault Diagnosis of MOS Combinational Networks. IEEE Trans. Computers 31(2): 129-139 (1982) - [c14]Yinghua Min, Stephen Y. H. Su:
Testing functional faults in VLSI. DAC 1982: 384-392 - [c13]Yashwant K. Malaiya, Stephen Y. H. Su:
A New Fault Model and Testing Technique for CMOS Devices. ITC 1982: 25-34 - 1981
- [j20]Yashwant K. Malaiya, Stephen Y. H. Su:
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. IEEE Trans. Computers 30(8): 600-604 (1981) - [j19]Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya:
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. IEEE Trans. Computers 30(12): 989-995 (1981) - [c12]Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya:
State Diagram Approach for Functional Testing of Control Section. ITC 1981: 433-446 - [c11]Stephen Y. H. Su, Yu-I Hsieh:
Testing Functional Faults in Digital Systems Described by Register Transfer Language. ITC 1981: 447-457 - 1980
- [j18]Stephen Y. H. Su, Edgar DuCasse:
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. IEEE Trans. Computers 29(3): 254-258 (1980) - [j17]Mark G. Karpovsky, Stephen Y. H. Su:
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. IEEE Trans. Computers 29(6): 523-527 (1980) - [c10]Mark G. Karpovsky, Stephen Y. H. Su:
Detecting bridging and stuck-at faults at input and output pins of standard digital components. DAC 1980: 494-505
1970 – 1979
- 1979
- [j16]Israel Koren, Stephen Y. H. Su:
Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults. IEEE Trans. Computers 28(7): 514-520 (1979) - [c9]Yashwant K. Malaiya, Stephen Y. H. Su:
A survey of methods for intermittent fault analysis. MARK 1979: 577-586 - 1978
- [j15]Stephen Y. H. Su, Israel Koren, Yashwant K. Malaiya:
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults. IEEE Trans. Computers 27(6): 567-570 (1978) - [j14]Yacoub M. El-Ziq, Stephen Y. H. Su:
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. IEEE Trans. Computers 27(10): 911-923 (1978) - [c8]John G. Yee, Stephen Y. H. Su:
A scheme for tolerating faulty data in real-time systems. COMPSAC 1978: 663-667 - 1977
- [j13]Stephen Y. H. Su:
Hardware Description Language Applications: An Introdiction and Prognosis. Computer 10(6): 10-13 (1977) - [j12]Richard J. Spillman, Stephen Y. H. Su:
Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks. IEEE Trans. Computers 26(12): 1242-1251 (1977) - [c7]Stephen Y. H. Su, Richard J. Spillman:
An overview of fault-tolerant digital system architecture. AFIPS National Computer Conference 1977: 19-26 - [c6]Yacoub M. El-Ziq, Stephen Y. H. Su:
Logic design automation of diagnosable MOS combinational logic networks. DAC 1977: 205-215 - 1976
- [j11]Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su:
Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers 25(1): 44-54 (1976) - 1975
- [j10]Stephen Y. H. Su:
An introduction to CHDL (computer hardware description languages). SIGARCH Comput. Archit. News 4(3): 22-23 (1975) - 1974
- [j9]Stephen Y. H. Su:
A survey of computer hardware description languages in the U.S.A. Computer 7(12): 45-51 (1974) - [j8]Stephen Y. H. Su:
Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973. SIGARCH Comput. Archit. News 3(3): 2-3 (1974) - [c5]Stephen Y. H. Su:
Speculation on the future of design automation. DAC 1974: 186-193 - 1973
- [j7]Stephen Y. H. Su:
B73-12 Fault Detection in Digital Circuits. IEEE Trans. Computers 22(5): 547 (1973) - [j6]Stephen Y. H. Su:
Review of "Fault Diagnosis of Digital Systems" by H. Y. Chang, E. G. Manning, and G. Metze. IEEE Trans. Syst. Man Cybern. 3(3): 301 (1973) - [j5]Stephen Y. H. Su:
Review of "Asynchronous Sequential Switching Circuits" by S. H. Unger. IEEE Trans. Syst. Man Cybern. 3(3): 302 (1973) - [c4]Stephen Y. H. Su:
An interactive design automation system. DAC 1973: 253-261 - 1972
- [j4]Stephen Y. H. Su, Yun-Chung Cho:
A New Approach to the Fault Location of Combinational Circuits. IEEE Trans. Computers 21(1): 21-30 (1972) - [j3]Stephen Y. H. Su, Achilles A. Sarris:
The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement. IEEE Trans. Computers 21(5): 479-485 (1972) - [j2]Stephen Y. H. Su, Peter T. Cheung:
Computer Minimization of Multivalued Switching Functions. IEEE Trans. Computers 21(9): 995-1003 (1972) - 1971
- [j1]Stephen Y. H. Su, Chong-Woo Nam:
Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints. IEEE Trans. Computers 20(12): 1445-1455 (1971) - [c3]Mehmet Baray, Stephen Y. H. Su:
A digital system modeling philosophy and design language. DAC 1971: 1-22 - [c2]Mehmet Baray, Stephen Y. H. Su, Robert L. Carberry:
The structure and operation of a design language compatible simulator. DAC 1971: 23-34 - [c1]Stephen Y. H. Su, Mehmet Baray, Robert L. Carberry:
A system modeling language translator. DAC 1971: 35-49
Coauthor Index
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