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2020 – today
- 2024
[c40]Wim Heirman, Stijn Eyerman:
Message from the Program Chairs; ISPASS 2024. ISPASS 2024: xii-xiii- [i2]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Accurate and Scalable Many-Node Simulation. CoRR abs/2401.09877 (2024) - 2023
- [j16]Sriram Aananthakrishnan
, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche:
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43(5): 78-87 (2023) - [c39]Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur:
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS 2023: 124-133 - 2022
- [c38]Alen Sabu, Harish Patil, Wim Heirman, Trevor E. Carlson:
LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications. HPCA 2022: 604-618 - [c37]Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout:
Scale-Model Architectural Simulation. ISPASS 2022: 58-68 - [c36]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS 2022: 322-331 - 2021
- [j15]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. 20(1): 78-81 (2021) - [j14]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. 20(2): 90-93 (2021) - [j13]Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout:
Scale-Model Simulation. IEEE Comput. Archit. Lett. 20(2): 175-178 (2021) - [j12]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. 18(3): 33:1-33:23 (2021) - [c35]Harish Patil, Alexander Isaev, Wim Heirman, Alen Sabu, Ali Hajiabadi, Trevor E. Carlson:
ELFies: Executable Region Checkpoints for Performance Analysis and Simulation. CGO 2021: 126-136 - [c34]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO 2021: 767-778 - 2020
- [j11]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. 19(1): 30-33 (2020) - [c33]Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur:
Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC 2020: 1-7 - [i1]Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz:
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR abs/2010.06277 (2020)
2010 – 2019
- 2018
- [j10]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. 17(1): 55-58 (2018) - [c32]Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur:
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT 2018: 28:1-28:11 - [c31]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS 2018: 179-188 - [c30]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur:
Many-core graph workload analysis. SC 2018: 22:1-22:11 - 2017
- [j9]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. 100: 30-41 (2017) - 2016
- [j8]Shoaib Akram, Jennifer B. Sartor, Kenzo Van Craeynest, Wim Heirman, Lieven Eeckhout:
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors. ACM Trans. Archit. Code Optim. 13(1): 4:1-4:25 (2016) - [c29]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers 2016: 365-368 - 2015
- [j7]Trevor E. Carlson, Siddharth Nilakantan, Mark Hempstead, Wim Heirman:
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization. IEEE Comput. Archit. Lett. 14(1): 30-33 (2015) - [c28]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout:
Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers 2015: 19:1-19:8 - [c27]Trevor E. Carlson, Wim Heirman, Osman Allam, Stefanos Kaxiras, Lieven Eeckhout:
The load slice core microarchitecture. ISCA 2015: 272-284 - 2014
- [j6]Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout:
An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. 11(3): 28:1-28:25 (2014) - [c26]Jennifer B. Sartor, Wim Heirman, Stephen M. Blackburn, Lieven Eeckhout, Kathryn S. McKinley:
Cooperative cache scrubbing. PACT 2014: 15-26 - [c25]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Undersubscribed threading on clustered cache architectures. HPCA 2014: 678-689 - [c24]Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. ROSS@ICS 2014: 7:1-7:7 - [c23]Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout:
BarrierPoint: Sampled simulation of multi-threaded applications. ISPASS 2014: 2-12 - 2013
- [j5]Chuntao Jiang, Zhibin Yu, Hai Jin, Cheng-Zhong Xu, Lieven Eeckhout, Wim Heirman, Trevor E. Carlson, Xiaofei Liao:
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling. ACM Trans. Archit. Code Optim. 10(4): 49:1-49:24 (2013) - [c22]Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout:
Fairness-aware scheduling on single-ISA heterogeneous multi-cores. PACT 2013: 177-187 - [c21]Trevor E. Carlson, Wim Heirman, Lieven Eeckhout:
Sampled simulation of multi-threaded applications. ISPASS 2013: 2-12 - [c20]Poona Bahrebar, Ruxandra-Marina Florea, Wim Heirman, Leon Denis, Adrian Munteanu, Dirk Stroobandt:
Making Communication a First-Class Citizen in Multicore Partitioning. PDP 2013: 287-293 - [c19]Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout:
Node Performance and Energy Analysis with the Sniper Multi-core Simulator. Parallel Tools Workshop 2013: 79-89 - 2012
- [c18]Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout:
Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT 2012: 3-12 - [c17]Thomas J. Ashby, Pieter Ghysels, Wim Heirman, Wim Vanroose:
The Impact of Global Communication Latency at Extreme Scales on Krylov Methods. ICA3PP (1) 2012: 428-442 - 2011
- [j4]Karel Bruneel, Wim Heirman, Dirk Stroobandt:
Dynamic data folding with parameterizable FPGA configurations. ACM Trans. Design Autom. Electr. Syst. 16(4): 43:1-43:29 (2011) - [c16]Zhe Ma, Trevor E. Carlson, Wim Heirman, Lieven Eeckhout:
Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy. Euro-Par Workshops (2) 2011: 272-281 - [c15]Wim Heirman, Trevor E. Carlson, Shuai Che, Kevin Skadron, Lieven Eeckhout:
Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads. IISWC 2011: 38-49 - [c14]Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout:
Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. PARCO 2011: 343-350 - [c13]Robbe Vancayseele, Brahim Al Farisi, Wim Heirman, Karel Bruneel, Dirk Stroobandt:
RecoNoC: A reconfigurable network-on-chip. ReCoSoC 2011: 1-2 - [c12]Trevor E. Carlson, Wim Heirman, Lieven Eeckhout:
Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. SC 2011: 52:1-52:12 - 2010
- [c11]Wim Heirman, Dirk Stroobandt, Narasinga Rao Miniskar, Roel Wuyts, Francky Catthoor:
PinComm: Characterizing Intra-application Communication for the Many-Core Era. ICPADS 2010: 500-507 - [c10]Atef Allam, Ian O'Connor, Wim Heirman:
Performance evaluation for passive-type Optical network-on-chip. International Symposium on Rapid System Prototyping 2010: 1-7
2000 – 2009
- 2009
- [j3]Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt:
Efficient memory management for hardware accelerated Java Virtual Machines. ACM Trans. Design Autom. Electr. Syst. 14(4): 48:1-48:18 (2009) - [c9]Peter Bertels, Wim Heirman, Dirk Stroobandt:
Strategies for dynamic memory allocation in hybrid architectures. Conf. Computing Frontiers 2009: 217-220 - [c8]Iñigo Artundo, Wim Heirman, Mikel Loperena, Christof Debaes, Jan M. Van Campenhout, Hugo Thienpont:
Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects. Hot Interconnects 2009: 163-169 - 2008
- [j2]Wim Heirman, Joni Dambre, Iñigo Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout:
Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems. Photonic Netw. Commun. 15(1): 25-40 (2008) - [c7]Peter Bertels, Wim Heirman, Dirk Stroobandt:
Efficient measurement of data flow enabling communication-aware parallelisation. IFMT 2008: 6 - [c6]Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout:
Rent's rule and parallel programs: characterizing network traffic behavior. SLIP 2008: 87-94 - 2007
- [j1]Wim Heirman, Joni Dambre, Iñigo Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout:
Predicting reconfigurable interconnect performance in distributed shared-memory systems. Integr. 40(4): 382-393 (2007) - [c5]Wim Heirman, Joni Dambre, Jan Van Campenhout:
Synthetic traffic generation as a tool for dynamic interconnect evaluation. SLIP 2007: 65-72 - 2006
- [c4]Iñigo Artundo, Daniel Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont:
Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior. ISPA Workshops 2006: 311-321 - [c3]Wim Heirman, Joni Dambre, Jan M. Van Campenhout:
Congestion modeling for reconfigurable inter-processor networks. SLIP 2006: 59-66 - 2005
- [c2]Wim Heirman, Joni Dambre, Jan Van Campenhout, Christof Debaes, Hugo Thienpont:
Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems. IPDPS 2005 - [c1]Wim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout:
Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. SLIP 2005: 51-58
Coauthor Index
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last updated on 2024-08-05 20:21 CEST by the dblp team
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