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ORCIDAndy Gean Ye
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2020 – today
- 2024
[j16]Sajjad Rostami Sani
, Andy Gean Ye:
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. ACM Trans. Reconfigurable Technol. Syst. 17(1): 17:1-17:29 (2024)- 2022
- [j15]Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye:
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs. Integr. 86: 30-43 (2022) - [j14]Sajjad Rostami Sani, Andy Gean Ye:
Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs. Microprocess. Microsystems 92: 104563 (2022) - [c19]Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye:
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. FCCM 2022: 1-9 - 2021
- [j13]Anas Razzaq, Andy Gean Ye:
Static power model for CMOS and FPGA circuits. IET Comput. Digit. Tech. 15(4): 263-278 (2021) - [j12]Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye:
Designing efficient FPGA tiles for power-constrained ultra-low-power applications. Integr. 78: 124-134 (2021) - 2020
- [c18]Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye:
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. FPL 2020: 214-219
2010 – 2019
- 2019
- [c17]Julien Li-Chee-Ming, Zheng Wu, Randy Tan, Ryan Tan, Naimul Mefraz Khan, Andy Gean Ye, Ling Guan:
A Scene-Based Augmented Reality Framework for Exhibits. ICIAR (1) 2019: 287-296 - 2018
- [j11]Farheen Fatima Khan, Andy Gean Ye:
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures. ACM Trans. Reconfigurable Technol. Syst. 11(1): 8:1-8:23 (2018) - 2017
- [j10]Farheen Fatima Khan, Andy Gean Ye:
A study on the accuracy of minimum width transistor area in estimating FPGA layout area. Microprocess. Microsystems 52: 287-298 (2017) - [c16]Andy Gean Ye, Karthik Ganesan:
Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only). FPGA 2017: 285 - 2016
- [j9]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye:
Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection. Circuits Syst. Signal Process. 35(7): 2487-2501 (2016) - [c15]Farheen Fatima Khan, Andy Gean Ye:
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. FPL 2016: 1-11 - 2015
- [c14]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye:
Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. ISCAS 2015: 2868-2871 - 2014
- [j8]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye, Saman Sadr:
New 2-D Eye-Opening Monitor for Gb/s Serial Links. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1209-1218 (2014) - [c13]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye:
A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links. ISCAS 2014: 2137-2140 - 2013
- [c12]Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye:
Two-dimensional eye-opening monitor for serial links. MWSCAS 2013: 181-184 - 2012
- [j7]Jasmina Vasiljevic, Andy Gean Ye:
Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays. IET Comput. Digit. Tech. 6(2): 95-104 (2012) - [j6]Jasmina Vasiljevic, Andy Gean Ye:
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding. Integr. 45(4): 427-438 (2012) - [j5]Shahin Sanayei Lotfabadi, Andy Gean Ye, Sridhar Krishnan:
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications. Microprocess. Microsystems 36(3): 151-158 (2012) - [j4]Omesh Mutukuda, Andy Gean Ye, Gul N. Khan:
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs. Microprocess. Microsystems 36(3): 167-175 (2012) - 2011
- [j3]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose:
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. 4(4): 32:1-32:23 (2011) - [c11]Hamid Asefi, Behnaz Ghoraani, Andy Gean Ye, Sridhar Krishnan:
Audio scene analysis using parametric signal features. CCECE 2011: 922-925 - [c10]Hamid Asefi, Behnaz Ghoraani, Andy Gean Ye, Sridhar Krishnan:
Hardware-software analysis of pole model features. CCECE 2011: 1288-1291 - 2010
- [j2]Andy Gean Ye:
Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 95-107 (2010) - [c9]Jasmina Vasiljevic, Andy Gean Ye:
A scalability study of fractional motion estimation for H.264 encoding. CCECE 2010: 1-5 - [c8]Omesh Mutukuda, Andy Gean Ye, Gul N. Khan:
The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources. FPT 2010: 216-223
2000 – 2009
- 2009
- [c7]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA 2009: 133-142 - 2006
- [j1]Andy Gean Ye, Jonathan Rose:
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 462-473 (2006) - 2005
- [c6]Andy Gean Ye, Jonathan Rose:
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. FPGA 2005: 3-13 - [c5]Andy Gean Ye, Jonathan Rose:
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. FPL 2005: 159-166 - 2004
- [c4]Andy Gean Ye, Jonathan Rose:
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. FPT 2004: 129-136 - 2003
- [c3]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC 2003: 61-64 - 2002
- [c2]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT 2002: 219-226
1990 – 1999
- 1999
- [c1]Andy Gean Ye, David M. Lewis:
Procedural Texture Mapping on FPGAs. FPGA 1999: 112-120
Coauthor Index
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