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ORCIDHiroyuki Mizuno
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2020 – today
- 2024
[j12]Shunsuke Minusa
, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. IEEE Access 12: 122929-122941 (2024)- [j11]Tadayuki Matsumura, Kanako Esaki, Shao Yang, Chihiro Yoshimura, Hiroyuki Mizuno:
Active Inference With Empathy Mechanism for Socially Behaved Artificial Agents in Diverse Situations. Artif. Life 30(2): 277-297 (2024) - [i9]Naoto Sato, Tomonori Sekiguchi, Takeru Utsugi, Hiroyuki Mizuno:
Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array. CoRR abs/2401.14683 (2024) - [i8]Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale. CoRR abs/2403.10136 (2024) - [i7]Kanako Esaki, Tadayuki Matsumura, Takeshi Kato, Shunsuke Minusa, Yang Shao, Hiroyuki Mizuno:
Environment-Centric Active Inference. CoRR abs/2408.12777 (2024) - 2023
- [j10]Takeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno:
Social Co-OS: Cyber-human social Co-operating system. IET Cyper-Phys. Syst.: Theory & Appl. 8(1): 1-14 (2023) - [c18]Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno:
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers. candar 2023: 196-202 - [c17]Kanako Esaki, Tadayuki Matsumura, Shunsuke Minusa, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno:
Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference. IWAI 2023: 14-28 - [c16]Hiroyuki Mizuno:
Quantum Computing from Hype to Game Changer. VLSI Technology and Circuits 2023: 1-4 - [i6]Yang Shao, Hirokazu Atsumori, Tadayuki Matsumura, Kanako Esaki, Shunsuke Minusa, Hiroyuki Mizuno:
The impact of individual information exchange strategies on the distribution of social wealth. CoRR abs/2304.00514 (2023) - [i5]Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi:
Mixbiotic society measures: Assessment of community well-going as living system. CoRR abs/2307.11594 (2023) - [i4]Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Yasuyuki Kudo, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi:
Mixbiotic society measures: Comparison of organizational structures based on communication simulation. CoRR abs/2307.15297 (2023) - 2022
- [c15]Kanako Esaki, Tadayuki Matsumura, Chihiro Yoshimura, Hiroyuki Mizuno:
Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability. SSCI 2022: 1036-1043 - [i3]Yang Shao, Quan Kong, Tadayuki Matsumura, Taiki Fuji, Kiyoto Ito, Hiroyuki Mizuno:
Mask Atari for Deep Reinforcement Learning as POMDP Benchmarks. CoRR abs/2203.16777 (2022) - 2021
- [c14]Kanako Esaki, Tadayuki Matsumura, Kiyoto Ito, Hiroyuki Mizuno:
Sensorimotor Visual Perception on Embodied System Using Free Energy Principle. PKDD/ECML Workshops (1) 2021: 865-877 - [i2]Takeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno:
Social Co-OS: Cyber-Human Social Co-Operating System. CoRR abs/2110.01861 (2021) - 2020
- [i1]Kanako Esaki, Tadayuki Matsumura, Kiyoto Ito, Hiroyuki Mizuno:
Sensorimotor Visual Perception on Embodied System Using Free Energy Principle. CoRR abs/2006.06192 (2020)
2010 – 2019
- 2016
- [j9]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. 6(2): 195-211 (2016) - [j8]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits 51(1): 303-309 (2016) - 2015
- [c13]Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR 2015: 542-546 - [c12]Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC 2015: 1-3 - 2014
- [c11]Tomonori Sadamoto, Kenji Kashima, Hiroshi Morita, Hiroyuki Mizuno:
Nonlinear reduced order modeling of plasticization cylinders. ACC 2014: 129-134 - 2013
- [c10]Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno:
Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD 2013: 1-4 - 2010
- [c9]Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno:
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6 - [c8]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [c7]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - 2008
- [c6]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - 2007
- [j7]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - [j6]Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno:
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. IEEE J. Solid State Circuits 42(4): 784-789 (2007) - 2006
- [c5]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c4]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209 - 2001
- [c3]Kiyoo Itoh, Hiroyuki Mizuno:
Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288
1990 – 1999
- 1999
- [j5]Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama:
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits 34(11): 1492-1500 (1999) - [j4]Hiroyuki Mizuno, Koichiro Ishibashi:
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 139-144 (1999) - [c2]Koichi Kise, Hiroyuki Mizuno, Masashi Yamaguchi, Keinosuke Matsumoto:
On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents. ICDAR 1999: 301-304 - 1998
- [c1]Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi:
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED 1998: 48-53 - 1997
- [j3]Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen:
A 1-V programmable DSP for wireless communications [CMOS]. IEEE J. Solid State Circuits 32(11): 1766-1776 (1997) - 1996
- [j2]Hiroyuki Mizuno, Takahiro Nagano:
Driving source-line cell architecture for sub-1-V high-speed low-power applications. IEEE J. Solid State Circuits 31(4): 552-557 (1996) - [j1]Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31(11): 1618-1624 (1996)
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