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2020 – today
- 2023
[j28]Umer Farooq
, Imran Baig, Muhammad Khurram Bhatti, Habib Mehrez, Arun Kumar, Manoj Gupta:
Prototyping using multi-FPGA platform: A novel and complete flow. Microprocess. Microsystems 96: 104751 (2023)- 2021
- [j27]Umer Farooq, Habib Mehrez:
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review. J. Electron. Test. 37(1): 7-24 (2021)
2010 – 2019
- 2018
- [j26]Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
Inter-FPGA interconnect topologies exploration for multi-FPGA systems. Des. Autom. Embed. Syst. 22(1-2): 117-140 (2018) - [j25]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Habib Mehrez:
Novel architectural space exploration environment for multi-FPGA based prototyping systems. Microprocess. Microsystems 56: 169-183 (2018) - 2017
- [j24]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25: 2044-2054 (2017) - [j23]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. J. Signal Process. Syst. 88(1): 1-12 (2017) - [c90]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS 2017: 572-579 - [c89]Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. ReConFig 2017: 1-6 - 2016
- [j22]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40: 16-26 (2016) - [c88]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Zouha Cherif, Maminionja Ravoson, Saqib Khan, Habib Mehrez:
Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. DSD 2016: 641-645 - [c87]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. CS2@HiPEAC 2016: 37-40 - [c86]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT 2016: 31-36 - [c85]Muhammad Moazam Azeem, Roselyne Chotin-Avot, Umer Farooq, Maminionja Ravoson, Habib Mehrez:
Multiple FPGAs based prototyping and debugging with complete design flow. IDT 2016: 171-176 - [c84]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS 2016: 104-111 - [c83]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid:
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP 2016: 635-642 - [c82]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez:
Inter-FPGA routing environment for performance exploration of multi-FPGA systems. RSP 2016: 107-113 - 2015
- [b1]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Lecture Notes in Electrical Engineering 350, Springer 2015, ISBN 978-3-319-19173-7, pp. 1-209 - [j21]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Des. Autom. Embed. Syst. 19(3): 223-242 (2015) - [j20]Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez:
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Comput. Digit. Tech. 9(5): 259-267 (2015) - [j19]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro 35(6): 48-59 (2015) - [c81]Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid:
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC 2015: 411-418 - 2014
- [j18]Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez:
MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. Int. J. Embed. Real Time Commun. Syst. 5(2): 43-60 (2014) - [j17]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Low cost solutions for secure remote reconfiguration of FPGAs. Int. J. Embed. Syst. 6(2/3): 257-265 (2014) - [j16]Alp Kiliç, Zied Marrakchi, Habib Mehrez:
A Top-Down Optimization Methodology for Mutually Exclusive Applications. Int. J. Reconfigurable Comput. 2014: 827613:1-827613:18 (2014) - [j15]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsystems 38(6): 526-538 (2014) - [j14]Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45(4): 355-366 (2014) - [j13]Boukary Ouattara, Lise Doyen, David Ney, Habib Mehrez, Pirouz Bazargan-Sabet:
Power grid redundant path contribution in system on chip (SoC) robustness against electromigration. Microelectron. Reliab. 54(9-10): 1702-1706 (2014) - [c80]Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC 2014: 1-7 - [c79]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. ARC 2014: 13-24 - [c78]Nidhameddine Belhadj, Mohamed Ali Ben Ayed, Nouri Masmoudi, Zied Marrakchi, Habib Mehrez:
MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. ATSIP 2014: 153-157 - [c77]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez:
Power consumption analysis for mesh based FPGA. DTIS 2014: 1-5 - [c76]Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq:
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS 2014: 1-6 - [c75]Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. FCCM 2014: 125-132 - [c74]Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang:
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA 2014: 242 - [c73]Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only). FPGA 2014: 251 - [c72]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c71]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL 2014: 1-4 - [c70]Alp Kiliç, Delaram Haghighitalab, Habib Mehrez, Hassan Aboushady:
Low-power comb decimation filter for RF Sigma-Delta ADCs. ISCAS 2014: 1596-1599 - [c69]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - [c68]Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
A reference-based specification tool for creating reliable library development specifications. NEWCAS 2014: 133-136 - [c67]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. ReConFig 2014: 1-6 - [c66]Qingshan Tang, Habib Mehrez, Matthieu Tuna:
Multi-FPGA prototyping board issue: the FPGA I/O bottleneck. ICSAMOS 2014: 207-214 - [c65]Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi:
On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC 2014: 64-69 - [c64]Abdulfattah Mohammad Obeid, Syed Manzoor Qasim, Mohammed S. BenSaleh, Zied Marrakchi, Habib Mehrez, Heni Ghariani, Mohamed Abid:
Flexible reconfigurable architecture for DSP applications. SoCC 2014: 204-209 - 2013
- [j12]Emna Amouri, Habib Mehrez, Zied Marrakchi:
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. 2013: 802436:1-802436:24 (2013) - [j11]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. Int. J. Reconfigurable Comput. 2013: 853510:1-853510:12 (2013) - [j10]Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. Integr. 46(2): 104-118 (2013) - [j9]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. Microelectron. J. 44(12): 1052-1062 (2013) - [j8]Arwa Ben Dhia, Samuel N. Pagliarini, Lirida Alves de Barros Naviner, Habib Mehrez, Philippe Matherat:
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectron. Reliab. 53(9-11): 1189-1193 (2013) - [c63]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC 2013: 1-8 - [c62]Nidhameddine Belhadj, Nejmeddine Bahri, Mohamed Ali Ben Ayed, Zied Marrakchi, Habib Mehrez:
Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. SSD 2013: 1-4 - [c61]Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC 2013: 197-209 - [c60]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC 2013: 210-217 - [c59]Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez:
Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC 2013: 221 - [c58]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips 2013: 1-3 - [c57]Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi:
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld 2013: 3:1-3:6 - [c56]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT 2013: 334-337 - [c55]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi:
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c54]Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi:
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI 2013: 335-336 - [c53]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT 2013: 223-226 - [c52]Mariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid:
Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. ISSoC 2013: 1-4 - [c51]Jung Kyu Chae, Severine Bertrand, Pierre-Francois Ollagnon, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
Efficient state-dependent power model for multi-bit flip-flop banks. MWSCAS 2013: 461-464 - [c50]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Efficient AES-GCM for VPNs using FPGAs. MWSCAS 2013: 1411-1414 - [c49]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Protecting FPGA bitstreams using authenticated encryption. NEWCAS 2013: 1-4 - [c48]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS 2013: 1-4 - [c47]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Lightweight and compact solutions for secure reconfiguration of FPGAs. ReConFig 2013: 1-4 - [c46]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Improved method for parallel AES-GCM cores using FPGAs. ReConFig 2013: 1-4 - [c45]Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi:
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig 2013: 1-6 - [c44]Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq:
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig 2013: 1-6 - [c43]Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Routing algorithm for multi-FPGA based systems using multi-point physical tracks. RSP 2013: 2-8 - [c42]Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
A formalism of the specifications for library development. SoCC 2013: 307-312 - [c41]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
High speed authenticated encryption for slow changing key applications using reconfigurable devices. Wireless Days 2013: 1-6 - 2012
- [j7]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocess. Microsystems 36(8): 588-605 (2012) - [c40]Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez:
A logic sharing synthesis tool for mutually exclusive applications. DTIS 2012: 1-6 - [c39]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Efficient parallel-pipelined GHASH for message authentication. ReConFig 2012: 1-6 - [c38]Mariem Turki, Habib Mehrez, Zied Marrakchi:
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig 2012: 1-6 - [c37]Qingshan Tang, Habib Mehrez, Matthieu Tuna:
Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. RSP 2012: 71-77 - 2011
- [j6]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfigurable Comput. 2011: 121404:1-121404:18 (2011) - [j5]Husain Parvez, Zied Marrakchi, Alp Kiliç, Habib Mehrez:
Application-Specific FPGA using heterogeneous logic blocks. ACM Trans. Reconfigurable Technol. Syst. 4(3): 24:1-24:14 (2011) - [c36]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229 - [c35]Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED 2011: 502-507 - [c34]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4 - 2010
- [c33]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010: 296-299 - [c32]Zied Marrakchi, Husain Parvez, Alp Kiliç, Habib Mehrez, Hmaied Marrakchi:
On the optimization of FPGA area depending on target applications. APCCAS 2010: 308-311 - [c31]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109 - [c30]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290 - [c29]Ludovic Noury, Habib Mehrez:
A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. ICECS 2010: 251-254 - [c28]Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez:
Routability driven placement for mesh-based FPGA architecture. IDT 2010: 85-90 - [c27]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Exploration of Heterogeneous FPGA Architectures. ReCoSoC 2010: 37-44
2000 – 2009
- 2009
- [j4]Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez:
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009: 259837:1-259837:13 (2009) - [c26]Husain Parvez, Zied Marrakchi, Habib Mehrez:
ASIF: Application Specific Inflexible FPGA. FPT 2009: 112-119 - [c25]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794 - [c24]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206 - 2008
- [j3]Ana Abril, Habib Mehrez, Frédéric Pétrot, Jean Gobert, Carolina Miro:
Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle. Tech. Sci. Informatiques 27(1-2): 203-233 (2008) - [c23]Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez:
A new coarse-grained FPGA architecture exploration environment. FPT 2008: 285-288 - [c22]Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez:
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326 - [c21]Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez:
Arithmetic Data Path Optimization Using Borrow-Save Representation. ISVLSI 2008: 4-9 - [c20]Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120 - [c19]Husain Parvez, Zied Marrakchi, Habib Mehrez:
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126 - 2007
- [c18]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT 2007: 269-272 - [c17]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252 - 2006
- [c16]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225 - [c15]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229 - [c14]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679 - [c13]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268 - [c12]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot:
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123 - 2005
- [c11]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005 - [c10]Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot:
Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62 - 2004
- [j2]Roselyne Avot-Chotin, Habib Mehrez:
Hardware Implementation of Discrete Stochastic Arithmetic. Numer. Algorithms 37(1-4): 21-33 (2004) - 2002
- [c9]Ana Belén Abril García, Jean Gobert, Thomas Dombek, Habib Mehrez, Frédéric Pétrot:
Cycle-accurate energy estimation in system level descriptions of embedded systems. ICECS 2002: 549-552 - [c8]Roselyne Chotin, Habib Mehrez:
A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard. ICECS 2002: 603-606 - 2001
- [c7]Yann Bajot, Habib Mehrez:
Customizable DSP architecture for ASIP core design. ISCAS (4) 2001: 302-305 - [c6]Yannick Dumonteix, Yann Bajot, Habib Mehrez:
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. ISCAS (4) 2001: 878-881 - 2000
- [c5]Mourad Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot:
A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. CAMP 2000: 155-162 - [c4]Yannick Dumonteix, Habib Mehrez:
A family of redundant multipliers dedicated to fast computation for signal processing. ISCAS 2000: 325-328
1990 – 1999
- 1998
- [j1]Mourad Aberbour, A. Houelle, Habib Mehrez, Nicolas Vaucher, Alain Guyot:
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 114-121 (1998) - 1997
- [c3]Mourad Aberbour, Anne Derieux, Habib Mehrez, Nicolas Vaucher:
Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries. MSE 1997: 81-82 - 1995
- [c2]A. Houelle, Habib Mehrez, Nicolas Vaucher, Luis A. Montalvo, Alain Guyot:
Application of fast layout synthesis environment to dividers evaluation. IEEE Symposium on Computer Arithmetic 1995: 67-74 - [c1]Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher:
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. VLSI Design 1995: 386-391
Coauthor Index
Roselyne Chotin-Avot
aka: Roselyne Avot-Chotin
aka: Roselyne Avot-Chotin
[j24] [c90] [j22] [c86] [c84] [c83] [b1] [j21] [j20] [j19] [c81] [j18] [j16] [j14] [c80] [c78] [c77] [c76] [c74] [c69] [c65] [c64] [j12] [j11] [j9] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c48] [c45] [c44] [j7] [c40] [c38] [j6] [j5] [c36] [c34] [c33] [c32] [c31] [c30] [c28] [c27] [j4] [c26] [c25] [c24] [c23] [c22] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10]
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last updated on 2025-01-20 23:03 CET by the dblp team
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