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ORCIDTom J. Kazmierski
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2020 – today
- 2020
[c59]Ginés Doménech-Asensi, Tom J. Kazmierski:
High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors. DATE 2020: 646-649- [c58]Matthew Johns, Tom J. Kazmierski:
A Minimal RISC-V Vector Processor for Embedded Systems. FDL 2020: 1-4 - [c57]Ginés Doménech-Asensi, Tom J. Kazmierski:
Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs. ISCAS 2020: 1-5 - [c56]Michail Pligouroudis, Rafael Angel Gutierrez Nuno, Tom J. Kazmierski:
Modified Compressed Sparse Row Format for Accelerated FPGA-Based Sparse Matrix Multiplication. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j8]Yunpeng Cai
, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski:
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 550-559 (2019) - [c55]Ginés Doménech-Asensi, Tom J. Kazmierski:
Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors. FDL 2019: 1-4 - [c54]Ginés Doménech-Asensi, Tom J. Kazmierski:
An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. ISCAS 2019: 1-5 - [e2]Tom J. Kazmierski, Reinhard von Hanxleden, Terrence S. T. Mak:
2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019. IEEE 2019, ISBN 978-1-7281-4113-8 [contents] - 2018
- [c53]Yue Lu, Tom J. Kazmierski, Lianxi Liu:
A Bit-Serial Variable-Accuracy FFT Processor For Energy-Harvesting Systems. APCCAS 2018: 299-304 - [c52]Yue Lu, Shengyu Duan, Tom J. Kazmierski:
A New Ageing-Aware Approach Via Path Isolation. FDL 2018: 5-16 - [e1]Hiren D. Patel, Tom J. Kazmierski, Sebastian Steinhorst:
2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018. IEEE 2018, ISBN 978-1-5386-6418-6 [contents] - 2017
- [j7]Mauricio D. Gutierrez, Vasileios Tenentes, Daniele Rossi, Tom J. Kazmierski:
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance. J. Electron. Test. 33(4): 463-477 (2017) - [c51]Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi:
Low cost error monitoring for improved maintainability of IoT applications. DFT 2017: 1-6 - [c50]Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi:
Low power probabilistic online monitoring of systematic erroneous behaviour. ETS 2017: 1-2 - [c49]Ginés Doménech-Asensi, Tom J. Kazmierski:
Generation of new power processing structures exploiting genetic programming. ISIE 2017: 729-732 - [c48]Yue Lu, Tom J. Kazmierski:
Variable-accuracy bit-serial multiplication with row bypassing for ultra low power. NORCAS 2017: 1-6 - [c47]Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski:
Evaluation and analysis of single-phase clock flip-flops for NTV applications. PATMOS 2017: 1-6 - 2016
- [c46]Yue Lu, Tom J. Kazmierski:
An ultra-low-power variable-accuracy bit-serial FFT butterfly processing element for IoT sensors. APCCAS 2016: 13-16 - [c45]Yue Lu, Tom J. Kazmierski:
Error-free near-threshold adiabatic CMOS logic in presence of process variation. FDL 2016: 1-5 - [c44]Colin F. Snook, Tom J. Kazmierski:
Using event-B and Modelica to evaluate thermal management strategies in many core systems. FDL 2016: 1-5 - [c43]Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski:
Susceptible workload driven selective fault tolerance using a probabilistic fault model. IOLTS 2016: 115-120 - 2013
- [c42]Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett:
DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters. DATE 2013: 484 - [c41]Tom J. Kazmierski, Torsten Maehne:
Modeling communication and circuit's behavior. FDL 2013: 1 - [c40]Ime J. Umoh, Tom J. Kazmierski:
A floating gate graphene FET complementary inverter with symmetrical transfer characteristics. ISCAS 2013: 2071-2074 - 2012
- [j6]Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett:
An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 522-531 (2012) - [c39]Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Mansour Aloufi, Joseph Wenninger:
Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters. DATE 2012: 733-738 - [c38]Aleksandar Pajkanovic, Tom J. Kazmierski, Branko Dokic:
Minimum energy point of sub-threshold operated pass-transistor circuits. FDL 2012: 202-207 - 2011
- [j5]Alex S. Weddell, Geoff V. Merrett, Tom J. Kazmierski, Bashir M. Al-Hashimi:
Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 911-915 (2011) - [c37]Stefan Mahlknecht, Tom J. Kazmierski, Christoph Grimm, Leran Wang:
Wireless communication and energy harvesting in automobiles. DATE 2011: 1042-1047 - [c36]Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Alex S. Weddell, Geoff V. Merrett, Ivo Netali Ayala-Garcia:
Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique. DATE 2011: 1267-1272 - [c35]Chenxu Zhao, Tom J. Kazmierski:
An extension to SystemC-A to support mixed-technology systems with distributed components. DATE 2011: 1278-1284 - [c34]Ime J. Umoh, Tom J. Kazmierski:
VHDL-AMS model of a dual gate graphene FET. FDL 2011: 1-5 - 2010
- [j4]Neil Tisdale, Tom J. Kazmierski, Duncan Brooks:
Bandwidth selective filter for the pre-excision of narrowband interference in broadband beamformers. IET Commun. 4(2): 201-212 (2010) - [c33]Chenxu Zhao, Tom J. Kazmierski:
SystemC-A Modelling of Mixed-Technology Systems with Distributed Behaviour. FDL 2010: 105-110 - [c32]Chenxu Zhao, Tom J. Kazmierski:
Genetic-Based High-Level Synthesis of Sigma-Delta Modulator in SystemC-A. FDL 2010: 165-170 - [c31]Chenxu Zhao, Tom J. Kazmierski:
Genetic-based automated synthesis and optimization of MEMS accelerometers with sigma-delta control. ISCAS 2010: 901-904
2000 – 2009
- 2009
- [j3]Leran Wang, Tom J. Kazmierski:
VHDL-AMS Based Genetic Optimization of Mixed-Physical-Domain Systems in Automotive Applications. Simul. 85(10): 661-670 (2009) - [c30]Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Dibin Zhu:
An automated design flow for vibration-based energy harvester systems. DATE 2009: 1391-1396 - [c29]Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
HSPICE implementation of a numerically efficient model of CNT transistor. FDL 2009: 1-5 - [c28]Chenxu Zhao, Tom J. Kazmierski:
Analysis of sense finger dynamics for accurate ΣΔ MEMS accelerometer modelling in VHDL-AMS. FDL 2009: 1-4 - 2008
- [c27]Chenxu Zhao, Tom J. Kazmierski:
Automated Performance Optimisation and Layout Synthesis of MEMS Accelerometer with Sigma-Delta Force-Feedback Control Loop. BMAS 2008: 19-24 - [c26]Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density. DATE 2008: 146-151 - [c25]Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Russel N. Torah:
Integrated approach to energy harvester mixed technology modelling and performance optimisation. DATE 2008: 704-709 - [c24]Dafeng Zhou, Tom J. Kazmierski, Bashir M. Al-Hashimi:
VHDL-AMS Implementation of a Numerical Ballistic CNT Model. FDL (Selected Papers) 2008: 87-100 - [c23]Dafeng Zhou, Tom J. Kazmierski, Bashir M. Al-Hashimi:
VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation. FDL 2008: 94-98 - 2007
- [c22]Leran Wang, Chenxu Zhao, Tom J. Kazmierski:
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations. FDL 2007: 12-17 - [c21]Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
A fast, numerical circuit-level model of carbon nanotube transistor. NANOARCH 2007: 33-37 - 2006
- [j2]Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski:
Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2757-2764 (2006) - [c20]Hessa Al-Junaid, Tom J. Kazmierski:
HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope. DATE 2006: 644-645 - [c19]Hessa Al-Junaid, Tom J. Kazmierski, Leran Wang:
SystemC-A Modeling of an Automotive Seating Vibration Isolation System. FDL 2006: 107-113 - 2005
- [c18]Xianqiang Ren, Tom J. Kazmierski:
Linearly graded behavioural analogue performance models. FDL 2005: 147-153 - [c17]M. Burford, Tom J. Kazmierski:
A VHDL-AMS based Time-Domain Skin Depth Model. FDL 2005: 197-209 - [c16]Leran Wang, Tom J. Kazmierski:
VHDL-AMS modeling of an automotive vibration isolation seating system. Circuits, Signals, and Systems 2005: 160-164 - 2004
- [c15]Peter R. Wilson, J. Neil Ross, Andrew D. Brown, Tom J. Kazmierski, Jerzy Baranowski:
Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS. DATE 2004: 742-743 - [c14]Peter R. Wilson, Tom J. Kazmierski:
A novel approach to mixed-domain behavioral modeling of ferromagnetic hysteresis in VHDL-AMS. FDL 2004: 76-80 - [c13]Tom J. Kazmierski, Fazrena A. Hamid:
Behavioral modelling of RF filters in VHDL-AMS for automated architectural and parametric optimization. ISCAS (1) 2004: 81-84 - [c12]Hessa Al-Junaid, Tom J. Kazmierski:
SEAMS - a SystemC environment with analog and mixed-signal extensions. ISCAS (5) 2004: 281-284 - 2003
- [c11]Tom J. Kazmierski, Xing Q. Yang:
A Secure Web-Based Framework for Electronic System Level Design. DATE 2003: 11140-11143 - [c10]C. Isaia, Tom J. Kazmierski:
SystemC - a powerful system-level modelling platform for digital and mixed-signal hardware/software co-design. FDL 2003: 45-54 - [c9]Tom J. Kazmierski, Hessa Al-Junaid:
Synchronization of analogue and digital solvers in mixed-signal simulation on a SystemC platform. FDL 2003: 65-72 - [c8]Fazrena A. Hamid, Tom J. Kazmierski:
FIST - a VHDL-AMS based architectural synthesis strategy for integrated high-frequency analogue filters. FDL 2003: 163-175 - 2002
- [c7]Tom J. Kazmierski, Neil Clayton:
A Two-Tier Distributed Electronic Design Framework. DATE 2002: 227-231 - [c6]J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski:
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. ISCAS (4) 2002: 77-80 - [c5]Fazrena A. Hamid, Tom J. Kazmierski:
Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees. ISCAS (1) 2002: 749-752
1990 – 1999
- 1998
- [c4]Tom J. Kazmierski:
A Formal Description of VHDL-AMS Analogue Systems. DATE 1998: 916-920 - [c3]Tom J. Kazmierski:
Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation. DATE 1998: 941-944 - [c2]David Parsons, Tom J. Kazmierski:
Run Time Reusability in Object-Oriented Schematic Capture. ECOOP Workshops 1998: 561-562 - 1992
- [j1]Andrew D. Brown, Mark Zwolinski, Ken G. Nichols, Tom J. Kazmierski:
Confidence in mixed-mode circuit simulation. Comput. Aided Des. 24(2): 115-118 (1992) - 1991
- [c1]Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski:
A General Purpose Network Solving System. VLSI 1991: 147-156
Coauthor Index
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