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Soo-Ik Chae
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2020 – today
- 2021
- [j27]Youngkyu Choi
, Hyuk-Jae Lee
, Soo-Ik Chae:
High Throughput CBAC Hardware Encoder With Bin Merging for AVS 2.0 Video Coding. IEEE Trans. Circuits Syst. Video Technol. 31(11): 4439-4453 (2021)
2010 – 2019
- 2019
- [j26]Youngkyu Choi, Hyuk-Jae Lee, Soo-Ik Chae:
An adaptive hash-based search for integer motion estimation in SCC. IEICE Electron. Express 16(1): 20181019 (2019) - 2018
- [j25]Tae Sung Kim
, Chae-Eun Rhee
, Hyuk-Jae Lee
, Soo-Ik Chae:
Fast Integer Motion Estimation With Bottom-Up Motion Vector Prediction for an HEVC Encoder. IEEE Trans. Circuits Syst. Video Technol. 28(12): 3398-3411 (2018) - 2016
- [c44]Woo Seok Jeong, Hyunmin Jung, Soo-Ik Chae:
Decoding of main 4: 2: 2 10-bit bitstreams in HEVC Main 8-bit best-effort decoders. ICCE 2016: 223-224 - 2015
- [c43]Hyunmin Jung, Soonwoo Choi, Soo-Ik Chae:
Coding efficiency of the context-based arithmetic coding engine of AVS 2.0 in the HEVC encoder. ICCE 2015: 377-378 - [c42]Jing Cui, Youngkyu Choi, Soo-Ik Chae:
Coding efficiency of AVS 2.0 for CBAC and CABAC engines. ICMV 2015: 98751Q - 2013
- [j24]Greg Atwood, Soo-Ik Chae, Simon S. Y. Shim:
Next-Generation Memory [Guest editors' introduction]. Computer 46(8): 21-22 (2013) - [j23]Soonwoo Choi, Jicheon Kim, Soo-Ik Chae:
Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders. IEEE Trans. Consumer Electron. 59(3): 592-597 (2013) - [c41]Soonwoo Choi, Seunggyu Jeoung, Jicheon Kim, Soo-Ik Chae:
Generation of efficient bitstreams for functional tests of video decoders. ICCE 2013: 566-567 - 2011
- [j22]Daewoong Kim, Kilhyung Cha, Doo-Seung Hong, Soonwoo Choi, Soo-Ik Chae:
A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models. EURASIP J. Embed. Syst. 2011 (2011) - 2010
- [j21]Moonmo Koo, Soo-Ik Chae:
Flexible DMA subsystem in multi-core platforms for video applications. IEICE Electron. Express 7(14): 1065-1071 (2010) - [j20]Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae:
Constrained-random bitstream generation for H.264/AVC decoder conformance test. IEEE Trans. Consumer Electron. 56(2): 848-855 (2010) - [c40]Soonwoo Choi, Jason Jong Kyu Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae:
A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor. SoCC 2010: 105-108
2000 – 2009
- 2009
- [j19]Jinhyun Cho, Doowon Lee, Sang-yong Yoon, Sanggyu Park, Soo-Ik Chae:
VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(1): 279-290 (2009) - [j18]Daewoong Kim, Kilhyung Cha, Soo-Ik Chae:
Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator. IEICE Trans. Inf. Syst. 92-D(7): 1500-1502 (2009) - [j17]Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara
, Luigi Carro
, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan:
Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. Integr. 42(2): 227-245 (2009) - [j16]Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae:
A mixed-level virtual prototyping environment for SystemC-based design methodology. Microelectron. J. 40(7): 1082-1093 (2009) - [c39]Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae:
Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks. SiPS 2009: 173-178 - 2008
- [j15]Sanggyu Park, Do-sun Hong, Soo-Ik Chae:
A hardware operating system kernel for multi-processor systems. IEICE Electron. Express 5(9): 296-302 (2008) - [j14]Sang-yong Yoon, Soo-Ik Chae:
Cache Optimization for H.264/AVC Motion Compensation. IEICE Trans. Inf. Syst. 91-D(12): 2902-2905 (2008) - [j13]Daewoong Kim, Kilhyung Cha, Soo-Ik Chae:
A high-performance OpenVG accelerator with dual-scanline filling rendering. IEEE Trans. Consumer Electron. 54(3): 1303-1311 (2008) - [c38]Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae:
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. FDL 2008: 251-252 - 2007
- [j12]Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara
, Luigi Carro
, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya:
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. Des. Autom. Embed. Syst. 11(4): 249-283 (2007) - [c37]Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya:
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. DAC 2007: 39-42 - [c36]Lisane B. de Brisolara
, Sang-Il Han, Xavier Guerin, Luigi Carro
, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya:
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. SCOPES 2007: 81-89 - 2006
- [j11]Seokkee Kim, Soo-Ik Chae:
A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications. IEICE Trans. Electron. 89-C(5): 649-652 (2006) - [c35]Ren Huang, Soo-Ik Chae:
Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring. CIT 2006: 179 - [c34]Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae:
Reusable component IP design using refinement-based design environment. ASP-DAC 2006: 588-593 - [c33]Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya:
Functional modeling techniques for efficient SW code generation of video codec applications. ASP-DAC 2006: 935-940 - [c32]Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya:
Buffer memory optimization for video codec application modeled in Simulink. DAC 2006: 689-694 - [c31]Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae:
A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. IEEE International Workshop on Rapid System Prototyping 2006: 63-68 - 2005
- [j10]Eunseok Song, Yido Koo, Yeon-Jae Jung, Deok-Hee Lee, Sangyoung Chu, Soo-Ik Chae:
A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan. IEEE J. Solid State Circuits 40(5): 1094-1106 (2005) - [c30]Minho Kim, Ingu Hwang, Soo-Ik Chae:
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. ASP-DAC 2005: 631-634 - [c29]Seokkee Kim, Soo-Ik Chae:
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. Conf. Computing Frontiers 2005: 421-426 - [c28]Seokkee Kim, Soo-Ik Chae:
Complexity reduction in an nRERL microprocessor. ISLPED 2005: 180-185 - [c27]Sanggyu Park, Soo-Ik Chae:
A Two-Week Program for a Platform-Based SoC Design. MSE 2005: 43-44 - [c26]Sanggyu Park, Soo-Ik Chae:
A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. IEEE International Workshop on Rapid System Prototyping 2005: 237-239 - 2004
- [j9]Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee, Donghyeon Seo, Inho Song, Sanghun Jung, Joonbae Park, Deog-Kyoon Jeong, Soo-Ik Chae, W. Kim:
A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b. IEEE J. Solid State Circuits 39(7): 1185-1190 (2004) - [j8]Eunseok Song, Seung-Wook Lee, Jeong-Woo Lee, Joonbae Park, Soo-Ik Chae:
A reset-free anti-harmonic delay-locked loop using a cycle period detector. IEEE J. Solid State Circuits 39(11): 2055-2061 (2004) - [c25]Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya:
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. DAC 2004: 250-255 - [c24]Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae:
A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. PATMOS 2004: 159-168 - 2003
- [j7]Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae:
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Des. Autom. Embed. Syst. 8(2-3): 119-138 (2003) - [c23]Eunseok Song, In-Chan Choi, Young-Kil Park, Soo-Ik Chae:
A cycle-accurate joulemeter for CMOS VLSI circuits. ESSCIRC 2003: 619-622 - 2001
- [j6]Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi:
Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 377-383 (2001) - [c22]Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae:
An 8-b nRERL microprocessor for ultra-low-energy applications. ASP-DAC 2001: 27-28 - 2000
- [j5]Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
nMOS reversible energy recovery logic for ultra-low-energy applications. IEEE J. Solid State Circuits 35(6): 865-875 (2000) - [c21]Joonho Lim, Dong-Gyu Kim, Sang-Chul Kang, Soo-Ik Chae:
An 8×8 nRERL serial multiplier for ultra-low-power aplications. ASP-DAC 2000: 35-36 - [c20]Kyungmin Na, Kyung Jin Lee, Soo-Ik Chae:
Frequency-domain separation of convolved non-stationary signals with adaptive non-causal FIR filters. EUSIPCO 2000: 1-4 - [c19]Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae:
A three-port nRERL register file for ultra-low-energy applications. ISLPED 2000: 161-166 - [c18]Koichi Nose, Soo-Ik Chae, Takayasu Sakurai:
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230 - [c17]Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae:
Emulator Environment Based on an FPGA Prototyping Board. IEEE International Workshop on Rapid System Prototyping 2000: 72-77
1990 – 1999
- 1999
- [j4]Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. IEEE J. Solid State Circuits 34(6): 898-903 (1999) - 1998
- [j3]Eel-Wan Lee, Soo-Ik Chae:
Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality. IEEE Trans. Pattern Anal. Mach. Intell. 20(5): 562-566 (1998) - [j2]Seongsoo Lee, Jeong-Min Kim, Soo-Ik Chae:
New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding. IEEE Trans. Circuits Syst. Video Technol. 8(6): 734-744 (1998) - [c16]Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi:
Partial bus-invert coding for power optimization of system level bus. ISLPED 1998: 127-129 - 1997
- [c15]Sungjun Park, Joonho Lim, Soo-Ik Chae:
Digital implementation of discrete-time cellular neural networks with distributed arithmetic. ICNN 1997: 959-963 - [c14]Sungjun Park, Soo-Ik Chae:
Improved sufficient convergence condition for the discrete-time cellular neural networks. ICNN 1997: 1158-1161 - [c13]Kyungmin Na, Soo-Ik Chae:
Single-sensor active noise cancellation using recurrent neural network predictors. ICNN 1997: 2153-2156 - 1996
- [c12]Kyungmin Na, Soo-Ik Chae:
GPD training of the state weighting functions in hidden control neural network. ICASSP 1996: 3366-3369 - [c11]Sun-Young Choi, Soo-Ik Chae:
Fast vector quantizer using multiple sorted index tables. ICIP (3) 1996: 443-446 - [c10]Seongsoo Lee, Soo-Ik Chae:
Two-step motion estimation algorithm using low-resolution quantization. ICIP (3) 1996: 795-798 - 1995
- [j1]Eel-Wan Lee, Soo-Ik Chae:
New Perceptron Model Using Random Bitstreams. Neural Comput. 7(2): 280-283 (1995) - [c9]Eel-Wan Lee, Soo-Ik Chae:
New classifier with reduced computational complexity. ICNN 1995: 968-973 - [c8]Joonho Lim, Soo-Ik Chae:
Ratio pulse arithmetic for radial basis function network. ICNN 1995: 1492-1495 - [c7]KyungMin Na, Soo-Ik Chae, SouGuil Ann:
Corrective training of hidden control neural network. ICNN 1995: 2867-2870 - [c6]Kyungmin Na, Bumki Jeon, Dong-Il Chang, Soo-Ik Chae, Souguil Ann:
Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method. EUROSPEECH 1995: 97-100 - [c5]Kyungmin Na, Jekwan Ryu, Dong-Il Chang, Soo-Ik Chae, Souguil Ann:
Recurrent neural prediction models for speech recognition. EUROSPEECH 1995: 2213-2216 - 1994
- [c4]Sungjun Park, Seung-Jai Min, Soo-Ik Chae:
Stereo Correspondence with Discrete-Time Cellular Neural Networks. ISCAS 1994: 225-228 - [c3]Joonho Lim, Eel-Wan Lee, Soo-Ik Chae:
Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. ISCAS 1994: 327-330 - [c2]Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae:
A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. ISCAS 1994: 471-474 - 1993
- [c1]Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae:
Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. ISCAS 1993: 1897-1900
Coauthor Index
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