"Modeling and optimization approach to robust and low-power FinFET SRAM ..."

Aditya Bansal, Saibal Mukhopadhyay, Kairshik Roy (2005)

> Home

Details and statistics

DOI: 10.1109/CICC.2005.1568799

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/BansalMR05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/BansalMR05
Aditya Bansal, Saibal Mukhopadhyay, Kairshik Roy:
Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era. CICC 2005: 835-838

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.