"Accelerating low bit-width convolutional neural networks with embedded FPGA."

Li Jiao et al. (2017)

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DOI: 10.23919/FPL.2017.8056820

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-06

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  dblp key:
  - conf/fpl/JiaoLCZW17
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  - https://dblp.org/rec/conf/fpl/JiaoLCZW17
Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang:
Accelerating low bit-width convolutional neural networks with embedded FPGA. FPL 2017: 1-4

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