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ORCIDI-Chyn Wey
Person information
- affiliation: Chang Gung University, Tao-Yuan, Taiwan
- affiliation (PhD 2008): National Taiwan University, Taipei, Taiwan
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2020 – today
- 2024
[i2]Emil Goh, Maoyang Xiang, I-Chyn Wey, Tee Hui Teo:
From English to ASIC: Hardware Implementation with Large Language Model. CoRR abs/2403.07039 (2024)- [i1]Huan-Ke Hsu, I-Chyn Wey, T. Hui Teo:
SF-MMCN: A Low Power Re-configurable Server Flow Convolution Neural Network Accelerator. CoRR abs/2403.10542 (2024) - 2023
- [j20]Nicholas Phipps
, Jin-Jia Shang, Tee Hui Teo, I-Chyn Wey:
Pre-Computing Batch Normalisation Parameters for Edge Devices on a Binarized Neural Network. Sensors 23(12): 5556 (2023) - [j19]Hua-Pin Chen, I-Chyn Wey, Liang-Yen Chen, Cheng-Yueh Wu, San-Fu Wang:
Design and Verification of a New Universal Active Filter Based on the Current Feedback Operational Amplifier and Commercial AD844 Integrated Circuit. Sensors 23(19): 8258 (2023) - [c22]Huan-Ke Hsu, I-Chyn Wey, Tee Hui Teo:
A Energy-Efficient Re-configurable Multi-mode Convolution Neuron Network Accelerator. MCSoC 2023: 45-50 - [c21]Shih-Yi Yang, I-Chyn Wey, Huan-Ke Hsu, Tee Hui Teo:
A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology. MCSoC 2023: 154-159 - [c20]Tzu-Huan Huang, I-Chyn Wey, Emil Goh, Tee Hui Teo:
Convolutional Neural Networks Inference Accelerator Design using Selective Convolutional Layer. MCSoC 2023: 166-170 - [c19]Xuezhi Zhang, I-Chyn Wey, Maoyang Xiang, Tee Hui Teo:
Implementation of Physics Informed Neural Networks on Edge Device. MCSoC 2023: 441-445 - [c18]Chia-Chi Liu, I-Chyn Wey, Xuezhi Zhang, Tee Hui Teo:
Selective Pruning of Sparsity-Supported Energy-Efficient Accelerator for Convolutional Neural Networks. MCSoC 2023: 454-461 - 2022
- [c17]Shi Hui Chua, Tee Hui Teo, Mulat Ayinet Tiruye, I-Chyn Wey:
Systolic Array Based Convolutional Neural Network Inference on FPGA. MCSoC 2022: 128-133 - [c16]Tan Rong Loo, Tee Hui Teo, Mulat Ayinet Tiruye, I-Chyn Wey:
High-Performance Asynchronous CNN Accelerator with Early Termination. MCSoC 2022: 140-144 - [c15]Raman Maurya, Tee Hui Teo, Shi Hui Chua, Hwang-Cherng Chow, I-Chyn Wey:
Complex Human Activities Recognition Based on High Performance 1D CNN Model. MCSoC 2022: 330-336 - 2021
- [c14]Jhih-Syong Fong, Ya-Hui Chuang, Fu-Sheng Yu, I-Chyn Wey, San-Fu Wang:
Wearable Parkinson's Disease Finger Tapping Quantitative Evaluation Algorithm Combined with Impedance Sensing. SNPD 2021: 115-117 - 2020
- [j18]Yufeng Li, Yan Li, I-Chyn Wey, Deqiang Cheng, Fan Yang, Xuan Zeng, Jie Chen:
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. IEEE Trans. Circuits Syst. Video Technol. 30(10): 3803-3813 (2020)
2010 – 2019
- 2019
- [c13]I-Chyn Wey, Chun-Han Chen, Si-Zhan Fang, Heng-Jui Chou:
Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications. ICUFN 2019: 179-181 - 2018
- [j17]Yan Li, Yufeng Li, I-Chyn Wey, Jianhao Hu, Fan Yang, Xuan Zeng, Xiaoxue Jiang, Jie Chen:
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. IEEE J. Solid State Circuits 53(8): 2389-2398 (2018) - [j16]Bing-Chen Wu, I-Chyn Wey:
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 141-153 (2018) - 2017
- [j15]Xiaojian Yu, Kambiz Moez, I-Chyn Wey, Mohamad Sawan, Jie Chen:
A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 737-741 (2017) - 2016
- [j14]Lili Lin, I-Chyn Wey, Jing-Hua Ding:
Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification. Signal Image Video Process. 10(1): 171-180 (2016) - [c12]Xiaojian Yu, Kambiz Moez, I-Chyn Wey, Jie Chen:
Power management design for lab-on-chip biosensors. EMBC 2016: 2986-2989 - 2015
- [j13]Xin-Xiang Lian, I-Chyn Wey, Chien-Chang Peng, Zhi-Qun Cheng:
Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications. IEICE Electron. Express 12(3): 20141122 (2015) - [j12]I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Changhong Yu:
Robust C-element design for soft-error mitigation. IEICE Electron. Express 12(10): 20150268 (2015) - [j11]I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, Heng-Jui Chou:
Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique. Int. J. Circuit Theory Appl. 43(7): 854-865 (2015) - [j10]I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao:
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 78-87 (2015) - 2014
- [j9]I-Chyn Wey, Chien-Chang Peng, Heng-Jui Chou, Po Tsang Chen:
Reliable and low error dual modular redundancy FIR filter with wide protection window. IEICE Electron. Express 11(9): 20140183 (2014) - [j8]I-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow:
Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits. Int. J. Circuit Theory Appl. 42(5): 529-541 (2014) - [j7]I-Chyn Wey, Shu-Hao Kuo:
All digital folded low-area, low-power maximum power point tracking chip for photovoltaic energy conversion system. Int. J. Circuit Theory Appl. 42(9): 939-955 (2014) - [j6]I-Chyn Wey, Ye-Jhih Shen:
Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits. Integr. 47(4): 431-442 (2014) - [j5]I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng:
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron. J. 45(1): 1-13 (2014) - [c11]Chun-Yen Wu, Chi-Nan Chuang, Chao-Chyun Chen, I-Chyn Wey:
A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. GCCE 2014: 352-353 - 2013
- [j4]I-Chyn Wey, Yi-Jung Lan, Chien-Chang Peng:
Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design. Microelectron. Reliab. 53(12): 2057-2069 (2013) - 2012
- [j3]I-Chyn Wey, Chun-Chien Wang:
Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1923-1928 (2012)
2000 – 2009
- 2009
- [j2]I-Chyn Wey, You-Gang Chen, Changhong Yu, An-Yeu Wu, Jie Chen:
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(11): 2411-2424 (2009) - 2008
- [j1]I-Chyn Wey, You-Gang Chen, An-Yeu Wu:
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1708-1712 (2008) - [c10]Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu:
An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. ISCAS 2008: 608-611 - 2007
- [c9]Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu:
Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS 2007: 869-872 - [c8]Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao:
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. ISCAS 2007: 1803-1806 - [c7]Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu:
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. SiPS 2007: 493-498 - 2006
- [c6]Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu:
A portable all-digital pulsewidth control loop for SOC applications. ISCAS 2006 - [c5]Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu:
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS 2006 - 2005
- [c4]I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu:
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) 2005: 1074-1077 - [c3]Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu:
A scalable DCO design for portable ADPLL designs. ISCAS (6) 2005: 5449-5452 - 2003
- [c2]Hwang-Cherng Chow, I-Chyn Wey:
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. ISCAS (5) 2003: 121-124 - 2002
- [c1]Hwang-Cherng Chow, I-Chyn Wey:
A 3.3 V 1 GHz high speed pipelined Booth multiplier. ISCAS (1) 2002: 457-460
Coauthor Index
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last updated on 2024-07-08 14:35 CEST by the dblp team
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