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- articleJanuary 2017
State reduction for efficient digital calibration of analog/RF integrated circuits
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 90, Issue 1Pages 65–79https://doi.org/10.1007/s10470-016-0880-4Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration ...
- research-articleFebruary 2016
Timing Error Tolerance in Small Core Designs for SoC Applications
IEEE Transactions on Computers (ITCO), Volume 65, Issue 2Pages 654–663https://doi.org/10.1109/TC.2015.2420562Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage\frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping ...
- research-articleOctober 2015
Scan chain based at-speed diagnosis in the presence of scan output compaction schemes
PCI '15: Proceedings of the 19th Panhellenic Conference on InformaticsPages 419–423https://doi.org/10.1145/2801948.2801956The use of scan chains in diagnosis operations turns to be an important yield enhancement factor in nanotechnologies. However, scan chain output compaction schemes drastically reduce the ability to effectively diagnose (locate) faults in a defective ...
- research-articleJune 2015
A current monitoring technique for IDDQ testing in digital integrated circuits
Integration, the VLSI Journal (INTG), Volume 50, Issue CPages 48–60https://doi.org/10.1016/j.vlsi.2015.01.005Although IDDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that ...
- research-articleMarch 2015
A method for the estimation of defect detection probability of analog/RF defect-oriented tests
DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & ExhibitionPages 1395–1400A method to realistically estimate the defect detection probability achieved by defect-oriented analog/RF integrated circuit tests at the circuit design level is presented in this paper. The proposed method also provides insight to the efficiency of the ...
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- research-articleMarch 2015
Fast deployment of alternate analog test using Bayesian model fusion
- John Liaperdos,
- Haralampos-G. Stratigopoulos,
- Louay Abdallah,
- Yiorgos Tsiatouhas,
- Angela Arapoyanni,
- Xin Li
DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & ExhibitionPages 1030–1035In this paper, we address the problem of limited training sets for learning the regression functions in alternate analog test. Typically, a large volume of real data needs to be collected from different wafers and lots over a long period of time to be ...
- research-articleOctober 2014
Timing Error Tolerance in Pipeline Based Core Designs
PCI '14: Proceedings of the 18th Panhellenic Conference on InformaticsPages 1–6https://doi.org/10.1145/2645791.2645797Timing error tolerance is of great importance in nanometer technology integrated circuits. Two new flip-flop designs are presented for timing error tolerance, which are characterized by low silicon area overhead and power consumption compared to the ...
- research-articleMay 2014
The Time Dilation Technique for Timing Error Tolerance
IEEE Transactions on Computers (ITCO), Volume 63, Issue 5Pages 1277–1286https://doi.org/10.1109/TC.2012.289Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also ...
- articleDecember 2013
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Journal of Electronic Testing: Theory and Applications (JELT), Volume 29, Issue 6Pages 795–804https://doi.org/10.1007/s10836-013-5419-3Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs ...
- research-articleSeptember 2013
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 32, Issue 9Pages 1383–1394https://doi.org/10.1109/TCAD.2013.2255128A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting ...
- articleJanuary 2013
A test and calibration strategy for adjustable RF circuits
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 74, Issue 1Pages 175–192https://doi.org/10.1007/s10470-012-9981-xA test and calibration strategy suitable for adjustable RF circuits is presented in this paper. Certain performance-affecting circuit elements are designed to be digitally controllable, providing the capability to adjust the performance characteristics ...
- ArticleJuly 2010
Timing error tolerance in nanometer ICs
IOLTS '10: Proceedings of the 2010 IEEE 16th International On-Line Testing SymposiumPages 283–288https://doi.org/10.1109/IOLTS.2010.5560189Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based ...
- articleJuly 2010
A built-in-test circuit for RF differential low noise amplifiers
IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCSPI), Volume 57, Issue 7Pages 1549–1558https://doi.org/10.1109/TCSI.2009.2035417This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, ...
- research-articleAugust 2008
A Current Mode, Parallel, Two-Rail Code Checker
IEEE Transactions on Computers (ITCO), Volume 57, Issue 8Pages 1032–1045https://doi.org/10.1109/TC.2008.59A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new checker is characterised by high testability, high speed operation and low silicon area ...
- ArticleJuly 2005
Fast, Parallel Two-Rail Code Checker with Enhanced Testability
IOLTS '05: Proceedings of the 11th IEEE International On-Line Testing SymposiumPages 149–156https://doi.org/10.1109/IOLTS.2005.29A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The new checker is characterised by high testability, high operating frequencies and low silicon area ...
- ArticleMarch 2005
A Built-In Self-Test Scheme for Differential Ring Oscillators
ISQED '05: Proceedings of the 6th International Symposium on Quality of Electronic DesignPages 448–452https://doi.org/10.1109/ISQED.2005.2In this paper a new Built-In Self-Test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults ...
- articleOctober 2004
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
Journal of Electronic Testing: Theory and Applications (JELT), Volume 20, Issue 5Pages 523–531https://doi.org/10.1023/B:JETT.0000042516.12841.36In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be ...
- articleApril 2004
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
Journal of Electronic Testing: Theory and Applications (JELT), Volume 20, Issue 2Pages 133–142https://doi.org/10.1023/B:JETT.0000023677.58861.81In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). The proposed test-circuit is capable of detecting hard (catastrophic) and soft (parametric) faults, injected in ...
- ArticleMarch 2003
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture ispresented that targets to overcome the excessive hardwareoverhead requirements in built-in current sensing basedtesting applications. Moreover, a technique that utilises theIEEE 1149.1 boundary scan ...
- ArticleJuly 2002
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing
Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for ...