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In electromigration degradation process the existingphysical defects on interconnect play a critical role bysignificantly accelerating the EM damage underincreased current density and elevated temperature. Inthis work the simulation models were upgraded ...

This paper presents a detailed analysis of the power-supplyvoltage (IR) drop scaling in DSM technologies. For the first time, the effectsof temperature, electromigration and interconnect technology scaling(including resistivity increase of Cu ...

We present a methodology for on-chip characterization ofthe pin-to-pin propagation delay of single standard cells.A periodic waveform is provided to an input pin of thestandard cell under characterization, while keeping allother inputs at non-...

Input vector control is an effective technique forreducing the leakage current of combinational VLSIcircuits when these circuits are in the sleep mode. In thispaper a design technique for applying the minimumleakage input to a sequential circuit is ...

We present a silicon-on-insulator (SOI) pass-transistor logic(PTL) gate with an active body bias control circuit and comparethe proposed PTL gate with other types of PTL gates with differentbody bias circuits in two different 0:13µm SOI ...

Oxide tunneling current in MOS transistors is fast becominga non-negligible component of power consumptionas gate oxides get thinner, and could become in the futurethe dominant leakage mechanism in sub-100nm CMOS circuits.In this paper, we present an ...

This paper describes the use of integer equations forhigh level modeling digital circuits for application offormal verification properties at this level. Mostformal verification methods use BDDs, as a low levelrepresentation of a design. BDD operations ...