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- research-articleSeptember 2024
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 9Pages 2674–2686https://doi.org/10.1109/TCAD.2024.3378600Optical proximity correction (OPC) is a widely used technique to enhance the printability of designs in various foundaries. Recently, there has been a growing interest in using rigorous numerical optimization and machine learning to improve the robustness ...
- research-articleJuly 2024
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 7Pages 2140–2150https://doi.org/10.1109/TCAD.2024.3361400Source mask optimization (SMO) is vital for mitigating lithography imaging distortions caused by shrinking critical dimensions in integrated circuit fabrication. However, the computational intensity of SMO, involving multiple integrals in Abbe’s ...
- research-articleNovember 2024
Massively Parallel AIG Resubstitution
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation ConferenceArticle No.: 157, Pages 1–6https://doi.org/10.1145/3649329.3655987Resubstitution is a flexible algorithmic framework for circuit restructuring that has been incorporated into many high-effort logic optimization flows. It is thus important to speed up resubstitution in order to obtain high-quality realizations of large-...
- research-articleNovember 2024
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation ConferenceArticle No.: 71, Pages 1–6https://doi.org/10.1145/3649329.3655983Composite Current Source (CCS) timing model plays an important role in modern static timing analysis (STA) because it precisely captures the timing behavior of a design at advanced nodes. However, CCS is extremely time-consuming due to its accurate but ...
- research-articleNovember 2024
EMOGen: Enhancing Mask Optimization via Pattern Generation
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation ConferenceArticle No.: 148, Pages 1–6https://doi.org/10.1145/3649329.3655680Layout pattern generation via deep generative models is a promising methodology for building practical large-scale pattern libraries. However, although improving optical proximity correction (OPC) is a major target of existing pattern generation methods, ...
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- short-paperJune 2024
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024Pages 511–515https://doi.org/10.1145/3649476.3658770Due to the lengthy design cycle, generating legal, diverse and valid layout patterns artificially to expand VLSI layout pattern libraries has become an important problem to solve in order to facilitate modern design-for-manufacturability (DFM) studies. ...
- research-articleJune 2024
A Multi-agent Generative Model for Collaborative Global Routing Refinement
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024Pages 383–389https://doi.org/10.1145/3649476.3658721With minimal compromises on other metrics, eliminating overflow and lowering congestion level of global routing results as much as possible is a crucial topic for reducing violations and hotspots in subsequent design phases. Different from current common ...
- research-articleJune 2024
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024Pages 433–439https://doi.org/10.1145/3649476.3658713Large-scale multi-FPGA prototyping platforms play an indispensable role in the functional verification of complex IC designs. The process of compiling circuit designs typically entails tasks such as partitioning, global placement and routing using a ...
- research-articleJune 2024
Xplace: An Extremely Fast and Extensible Placement Framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 6Pages 1872–1885https://doi.org/10.1109/TCAD.2023.3346291Placement serves as a fundamental step in VLSI physical design. Recently, GPU-based placer DREAMPlace <xref ref-type="bibr" rid="ref1">[1]</xref> demonstrated its superiority over CPU-based placers. In this work, we develop an extremely fast GPU-...
- invited-talkMarch 2024
ISPD 2024 Lifetime Achievement Award Bio
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPage 231https://doi.org/10.1145/3626184.3635282The 2024 International Symposium on Physical Design lifetime achievement award goes to Professor Martin D F Wong for his oustanding contributions in the field.
- research-articleMarch 2024
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 75–82https://doi.org/10.1145/3626184.3633322Face-to-face (F2F) stacked 3D IC is a promising alternative for scaling beyond Moore's Law. In F2F 3D ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource ...
- research-articleMarch 2024
L2O-ILT: Learning to Optimize Inverse Lithography Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 3Pages 944–955https://doi.org/10.1109/TCAD.2023.3323164Inverse lithography technique (ILT) is one of the most widely used resolution enhancement techniques (RETs) to compensate for the diffraction effect in the lithography process. However, ILT suffers from runtime overhead issues with the shrinking size of ...
- research-articleFebruary 2024
Towards automated RISC-V microarchitecture design with reinforcement learning
AAAI'24/IAAI'24/EAAI'24: Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence and Thirty-Sixth Conference on Innovative Applications of Artificial Intelligence and Fourteenth Symposium on Educational Advances in Artificial IntelligenceArticle No.: 2, Pages 12–20https://doi.org/10.1609/aaai.v38i1.27750Microarchitecture determines the implementation of a microprocessor. Designing a microarchitecture to achieve better performance, power, and area (PPA) trade-off has been increasingly difficult. Previous data-driven methodologies hold inappropriate ...
- research-articleApril 2024
CoPlace: Coherent Placement Engine with Layout-Aware Partitioning for 3D ICs
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 65–70https://doi.org/10.1109/ASP-DAC58780.2024.10473808The emerging technologies of 3D integrated circuits (3DICs) unveil a new avenue for expanding the design space into the 3D domain and present the opportunity to overcome the bottleneck of Moore's Law for the traditional 2DICs. Among various technologies, ...
- research-articleDecember 2023
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 1Article No.: 20, Pages 1–23https://doi.org/10.1145/3630013Microarchitecture parameters tuning is critical in the microprocessor design cycle. It is a non-trivial design space exploration (DSE) problem due to the large solution space, cycle-accurate simulators’ modeling inaccuracy, and high simulation runtime for ...
- research-articleDecember 2023
LithoBench: benchmarking AI computational lithography for semiconductor manufacturing
NIPS '23: Proceedings of the 37th International Conference on Neural Information Processing SystemsArticle No.: 1315, Pages 30243–30254Computational lithography provides algorithmic and mathematical support for resolution enhancement in optical lithography, which is critical for semiconductor manufacturing. The time-consuming lithography simulation and mask optimization processes limit ...
- research-articleNovember 2023
A GPU-Accelerated Framework for Path-Based Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 11Pages 4219–4232https://doi.org/10.1109/TCAD.2023.3272274As a key routine in static timing analysis (STA), path-based analysis (PBA) plays a very important role in refining the critical path report by reducing excessive slack pessimism. PBA is also well known for its long execution time, which makes it a hot ...
- research-articleOctober 2023
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU
- Wenqian Zhao,
- Yang Bai,
- Qi Sun,
- Wenbo Li,
- Haisheng Zheng,
- Nianjuan Jiang,
- Jiangbo Lu,
- Bei Yu,
- Martin D. F. Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 10Pages 3210–3223https://doi.org/10.1109/TCAD.2023.3241110Over the past few years, super-resolution (SR) processing has achieved astonishing progress along with the development of deep learning. Nevertheless, the rigorous requirement for real-time inference, especially for video tasks, leaves a harsh challenge ...
- research-articleOctober 2023
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 10Pages 3402–3411https://doi.org/10.1109/TCAD.2023.3239559In the lithography process, subresolution assist features (SRAFs), as an essential resolution enhancement technique (RET), is applied to improve the pattern fidelity and enlarge the process window. In this article, we propose a robust constraint-aware ...
- research-articleSeptember 2023
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 28, Issue 5Article No.: 74, Pages 1–23https://doi.org/10.1145/3597931Modern very large-scale integration (VLSI) design requires the implementation of integrated circuits using electronic design automation (EDA) tools. Due to the complexity of EDA algorithms, there are numerous tool parameters that have imperative impacts ...