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- research-articleJanuary 2025
Resiliency at scale: managing google's TPUv4 machine learning supercomputer
- Yazhou Zu,
- Alireza Ghaffarkhah,
- Hoang-Vu Dang,
- Brian Towles,
- Steven Hand,
- Safeen Huda,
- Adekunle Bello,
- Alexander Kolbasov,
- Arash Rezaei,
- Dayou Du,
- Steve Lacy,
- Hang Wang,
- Aaron Wisner,
- Chris Lewis,
- Henri Bahini
NSDI'24: Proceedings of the 21st USENIX Symposium on Networked Systems Design and ImplementationArticle No.: 42, Pages 761–774TPUv4 (Tensor Processing Unit) is Google's 3rd generation accelerator for machine learning training, deployed as a 4096-node supercomputer with a custom 3D torus interconnect. In this paper, we describe our experience designing and operating the software ...
- research-articleOctober 2018
Voltage-stacked GPUs: a control theory driven cross-layer solution for practical voltage stacking in GPUs
MICRO-51: Proceedings of the 51st Annual IEEE/ACM International Symposium on MicroarchitecturePages 390–402https://doi.org/10.1109/MICRO.2018.00039More than 20% of the available energy is lost in "the last centimeter" from the PCB board to the microprocessor chip due to inherent inefficiencies of power delivery subsystems (PDSs) in today's computing systems. By series-stacking multiple voltage ...
- research-articleJune 2018
Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators
DAC '18: Proceedings of the 55th Annual Design Automation ConferenceArticle No.: 43, Pages 1–6https://doi.org/10.1145/3195970.3196037Voltage stacking (VS) fundamentally improves power delivery efficiency (PDE) by series-stacking multiple voltage domains to eliminate explicit step-down voltage conversion and reduce energy loss along the power delivery path. However, it suffers from ...
- research-articleJune 2018
Efficient and Reliable Power Delivery in Voltage-Stacked Manycore System with Hybrid Charge-Recycling Regulators
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)Pages 1–6https://doi.org/10.1109/DAC.2018.8465914Voltage stacking (VS) fundamentally improves power delivery efficiency (PDE) by series-stacking multiple voltage domains to eliminate explicit step-down voltage conversion and reduce energy loss along the power delivery path. However, it suffers from ...
- research-articleJune 2017
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017Article No.: 1, Pages 1–6https://doi.org/10.1145/3061639.3062268Despite being employed in burgeoning efforts to improve power delivery efficiency, integrated voltage regulators (IVRs) have yet to be evaluated in a rigorous, systematic, or quantitative manner. To fulfill this need, we present Ivory, a high-level ...
- research-articleJanuary 2017
Ti-States: Power Management in Active Timing Margin Processors
Temperature inversion is a transistor-level effect that improves performance when temperature increases. This article presents a comprehensive measurement-based analysis on temperature inversion's implications on architecture design and power management ...
- research-articleOctober 2016
Ti-states: processor power management in the temperature inversion region
MICRO-49: The 49th Annual IEEE/ACM International Symposium on MicroarchitectureArticle No.: 55, Pages 1–13Temperature inversion is a transistor-level effect that can improve performance when temperature increases. It has largely been ignored in the past because it does not occur in the typical operating region of a processor, but temperature inversion is ...
- research-articleDecember 2015
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+
MICRO-48: Proceedings of the 48th International Symposium on MicroarchitecturePages 308–321https://doi.org/10.1145/2830772.2830824The traditional guardbanding approach to ensure processor reliability is becoming obsolete because it always over-provisions voltage and wastes a lot of energy. As a next-generation alternative, adaptive guardbanding dynamically adjusts chip clock ...
- research-articleAugust 2014
GPUVolt: modeling and characterizing voltage noise in GPU architectures
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and designPages 141–146https://doi.org/10.1145/2627369.2627605Voltage noise is a major obstacle in improving processor energy efficiency because it necessitates large operating voltage guardbands that increase overall power consumption and limit peak performance. Identifying the leading root causes of voltage ...
- ArticleDecember 2013
An Efficient Power-Aware Resource Scheduling Strategy in Virtualized Datacenters
ICPADS '13: Proceedings of the 2013 International Conference on Parallel and Distributed SystemsPages 110–117In the era of cloud computing, data centers are well-known to be bounded by the power wall issue. This issue lowers the profit of service providers and obstructs the expansions of data center's scale. As virtual machine's behavior was not explored ...
