Article

Accurate and scalable reliability analysis of logic circuits

Authors:

Mihir R. Choudhury,

Kartik MohanramAuthors Info & Claims

DATE '07: Proceedings of the conference on Design, automation and test in Europe

Pages 1454 - 1459

Published: 16 April 2007 Publication History

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Abstract

Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology alternatives. Reliability analysis of logic circuits is NP-hard because of the exponential number of inputs, combinations and correlations in gate failures, and their propagation and interaction at multiple primary outputs. By coupling probability theory with concepts from testing and logic synthesis, this paper presents accurate and scalable algorithms for reliability analysis of logic circuits. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed analysis technique.

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Cited By

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Ibrahim WAmer Hde Rango FRisco Martín J(2016)Critical nodes count algorithm for accurate input vectors reliability rankingProceedings of the Summer Computer Simulation Conference10.5555/3015574.3015593(1-7)Online publication date: 24-Jul-2016
https://dl.acm.org/doi/10.5555/3015574.3015593
Yu CAlaghi AHayes JHu A(2012)Scalable sampling methodology for logic simulationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429422(195-201)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429422
Choudhury MMohanram KSciuto D(2008)Approximate logic circuits for low overhead, non-intrusive concurrent error detectionProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403593(903-908)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403593
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Information & Contributors

Information

Published In

DATE '07: Proceedings of the conference on Design, automation and test in Europe

April 2007

1741 pages

ISBN:9783981080124

General Chair:
Rudy Lauwereins
IMEC and KULeuven, Belgium
,
Program Chair:
Jan Madsen
DTU, Denmark

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

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DATE07

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE07: Design, Automation and Test in Europe

April 16 - 20, 2007

Nice, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Design, Automation and Test in Europe

March 31 - April 2, 2025

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Ibrahim WAmer Hde Rango FRisco Martín J(2016)Critical nodes count algorithm for accurate input vectors reliability rankingProceedings of the Summer Computer Simulation Conference10.5555/3015574.3015593(1-7)Online publication date: 24-Jul-2016
https://dl.acm.org/doi/10.5555/3015574.3015593
Yu CAlaghi AHayes JHu A(2012)Scalable sampling methodology for logic simulationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429422(195-201)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429422
Choudhury MMohanram KSciuto D(2008)Approximate logic circuits for low overhead, non-intrusive concurrent error detectionProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403593(903-908)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403593
Krishnaswamy SMarkov IHayes JFix L(2008)On the role of timing masking in reliable logic circuit designProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391703(924-929)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391703
Krishnaswamy SPlaza SMarkov IHayes JGielen G(2007)Enhancing design robustness with reliability-aware resynthesis and logic simulationProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326104(149-154)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326104

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Reliability analysis of logic circuits

Efficient reliability evaluation of combinational and sequential logic circuits

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Reliability analysis of logic circuits

Efficient reliability evaluation of combinational and sequential logic circuits

Basic circuits for multi-valued sequential logic

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