article

Efficient reliability evaluation of combinational and sequential logic circuits

Author:

H. JahaniradAuthors Info & Claims

Journal of Computational Electronics, Volume 18, Issue 1

Pages 343 - 355

https://doi.org/10.1007/s10825-018-1288-4

Published: 01 March 2019 Publication History

Abstract

Reliability has become one of the major goals for designs based on emerging technologies. Therefore, reliability evaluation should be included in the design flow of logic integrated circuits. In this paper, a probability transfer matrix-based method is developed for reliability evaluation of combinational and sequential logic circuits. The proposed method for combinational circuits is based on correct and incorrect probabilities for the binary logic values (0 and 1) of the nodes of the circuit. In this method, the reconvergent fanouts problem is handled using the concept of correlation coefficients. The reliability evaluation of sequential logic circuits is carried out by first breaking the loops, followed by iterative application of the combinational method on the converted circuit. The accuracy and scalability of the proposed methods are proved by various simulations on ISCAS 85 and LGSynth91 benchmark circuits for the combinational method and on ISCAS 89 benchmark circuits for the sequential method. The results show less than 2 % average error for reliability estimation compared with Monte Carlo (MC) simulations, outperforming state-of-the-art methods in terms of reliability estimation and algorithm runtime.

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Cited By

Shi ZXiao JJiang JZhang YZhou Y(2024)ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337246143:8(2479-2492)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3372461
Menbari AJahanirad H(2022)A Low-cost BIST Design Supporting Offline and Online TestsJournal of Electronic Testing: Theory and Applications10.1007/s10836-022-05986-038:1(107-123)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s10836-022-05986-0
Rahimi HJahanirad H(2021)An evolutionary approach to implement logic circuits on three dimensional FPGAsExpert Systems with Applications: An International Journal10.1016/j.eswa.2021.114780174:COnline publication date: 15-Jul-2021
https://dl.acm.org/doi/10.1016/j.eswa.2021.114780

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Efficient reliability evaluation of combinational and sequential logic circuits
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Published In

cover image Journal of Computational Electronics

Journal of Computational Electronics Volume 18, Issue 1

Mar 2019

373 pages

ISSN:1569-8025

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Copyright © Copyright © 2019 Springer Science+Business Media, LLC, part of Springer Nature.

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 March 2019

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Cited By

Shi ZXiao JJiang JZhang YZhou Y(2024)ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337246143:8(2479-2492)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3372461
Menbari AJahanirad H(2022)A Low-cost BIST Design Supporting Offline and Online TestsJournal of Electronic Testing: Theory and Applications10.1007/s10836-022-05986-038:1(107-123)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s10836-022-05986-0
Rahimi HJahanirad H(2021)An evolutionary approach to implement logic circuits on three dimensional FPGAsExpert Systems with Applications: An International Journal10.1016/j.eswa.2021.114780174:COnline publication date: 15-Jul-2021
https://dl.acm.org/doi/10.1016/j.eswa.2021.114780
Jahanirad H(2021)Reliability Estimation of Logic Circuits at the Transistor LevelCircuits, Systems, and Signal Processing10.1007/s00034-020-01588-340:5(2507-2534)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1007/s00034-020-01588-3

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