research-article

Probabilistic decision diagrams for exact probabilistic analysis

Author:

Afshin AbdollahiAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 266 - 272

Published: 05 November 2007 Publication History

Abstract

A decision diagram based framework is proposed for representing the probabilistic behavior of circuits with faulty gates. We introduce Probabilistic decision diagrams (PDD) as an exact computational tool which along with vast expressive power holds many other useful properties such as space efficiency (on average) and efficient manipulation algorithms (polynomial in size.)

An algorithm for constructing the PDD for a circuit is proposed. Useful information about probabilistic behavior of the circuit (such as output error probability for arbitrary input probability distribution) can be directly extracted from the PDD representation. Experimental results demonstrate the effectiveness and applicability of the proposed approach.

References

[1]

International Technology Roadmap for Semiconductors, ITRS, 2006. http://public.itrs.net/

[2]

C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol.23, Jul.-Aug. 2003, pp. 14--19.

Digital Library

[3]

C. Yang, M. Ciesielski, and V. Singhal, "BDS: a BDD-based logic optimization system," in Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 92--97.

Digital Library

[4]

Afshin Abdollahi and Massoud Pedram, "Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams," Proc. of Design Automation and Test in Europe, Mar. 2006, pp. 317--322.

Digital Library

[5]

J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies (C. E. Shannon and J. McCarthy, eds.), pp. 43--98, Princeton Univ. Press, Princeton, N.J., 1954.

[6]

N. Pippenger, "Reliable Computation by Formulas in the Presence of Noise", IEEE Trans on Inf. Theory, vol. 34(2), pp. 194--197, 1988.

Digital Library

[7]

J. B. Gao, Yan Qi and J. A. B. Fortes, "Bifurcations and Fundamental Error Bounds for Fault-Tolerant Computations" IEEE Transactions on Nanotechnology, vol. 4--4 pp. 395--402, July 2005.

Digital Library

[8]

V. L. Levin, "Probability Analysis of Combination Systems and their Reliability, "Engin. Cybernetics, no 6. Nov-Dec. 1964, pp. 78--84.

[9]

K. N. Patel, J. P. Hayes, and I. L. Markov, "Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models," IWLS, May 2003, pp. 59--64.

[10]

S. Krishnaswamy, G. F. Viamontes, I. L. Markov, J. P. Hayes, "Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices," In Proc. of the Design, Automation and Test Europe Conference, March 2005, pp. 282--287.

Digital Library

[11]

T. Rejimon and S. Bhanja, "Scalable Probabilistic Computing Models using Bayesian Networks", IEEE Midwest Symposium on Circuits and Systems, pp. 712--715, July 2005.

[12]

R. I. Bahar, J. Mundy and J. Chan, "A Probabilistic Based Design Methodology for Nanoscale Computation", ICCAD, 2003, pp. 480--486.

Digital Library

[13]

C. Y. Lee, "Representation of Switching Circuits by Binary Decision Programs," Bell System Technical Journal, vol. 38, no. 4, 1959, pp. 985--999.

[14]

S. B. Akers, "Functional Testing with Binary Decision Diagrams," Annual Conference of Fault-Tolerant Computing, 1978, pp. 75--82.

[15]

R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. 35, 1986, pp. 677--691.

Digital Library

[16]

K. Brace, R. Rudell, and R. Bryant, "Efficient Implementation of a BDD Package," Design Automation Conference, 1990, pp. 40--45.

Digital Library

[17]

Y.-T. Lai, M. Pedram, and S. Vrudhula, "EVBDD-Based Algorithms for Integer Linear Programming, Spectral Transformation, and Function Decomposition," IEEE Transactions on Computer-Aided Design, vol. 8, 1994, pp. 959--975.

Digital Library

[18]

M. Jaeger, "Probabilistic decision graphs-combining verification and AI techniques for probabilistic inference," International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems archive, Volume 12, Issue SUPPLEMENT, 2004, pp. 19--42.

Digital Library

[19]

A. Shen, S. evadas and A. Ghosh, "Probabilistic manipulation of boolean functions using free boolean diagrams," IEEE transactions on computer-aided design of integrated circuits and systems, 1995, vol. 14, no1, pp. 87--95.

Digital Library

[20]

R. E. Bryant and Y. A. Chen., "Verification of Arithmetic Circuits with Binary Moment Diagrams," Proceedings of 32th Design Automation Conference, 1995, pp 535--541.

Digital Library

[21]

R. Drechsler, B. Becker and S. Ruppertz, "The K*BMD: A Verification Data Structure," IEEE Design and Test of Computers 14(2), 1997, pp. 51--59.

Digital Library

Cited By

Jahanirad H(2019)Efficient reliability evaluation of combinational and sequential logic circuitsJournal of Computational Electronics10.1007/s10825-018-1288-418:1(343-355)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s10825-018-1288-4
Li MHsiao MRosenstiel WMacii E(2012)RAGProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492787(316-319)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492787
Luckenbill SLee JHu YMajumdar RHe LDe Micheli GAl-Hashimi BMueller WMacii E(2010)RALF: reliability analysis for logic faultsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871113(783-788)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871113
Show More Cited By

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Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

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Published: 05 November 2007

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Jahanirad H(2019)Efficient reliability evaluation of combinational and sequential logic circuitsJournal of Computational Electronics10.1007/s10825-018-1288-418:1(343-355)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s10825-018-1288-4
Li MHsiao MRosenstiel WMacii E(2012)RAGProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492787(316-319)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492787
Luckenbill SLee JHu YMajumdar RHe LDe Micheli GAl-Hashimi BMueller WMacii E(2010)RALF: reliability analysis for logic faultsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871113(783-788)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871113
Chen HHan JBahar RLombardi FAtienza DBrunvand E(2010)Stochastic computational models for accurate reliability evaluation of logic circuitsProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785497(61-66)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785497

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