research-article

RALF: reliability analysis for logic faults: an exact algorithm and its applications

Authors:

Samuel Luckenbill,

Rupak Majumdar,

Lei HeAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 783 - 788

Published: 08 March 2010 Publication History

Abstract

Reliability analysis for a logic circuit is one of the primary tasks in fault-tolerant logic synthesis. Given a fault model, it quantifies the impact of faults on the full-chip fault rate. We present RALF, an exact algorithm for calculating the reliability of a logic circuit. RALF is based on the compilation of a circuit to deterministic decomposable negation normal form (d-DNNF), a representation for Boolean formulas that can be more succinct than BDDs. Our algorithm can solve a large set of MCNC benchmark circuits within 5 minutes, enabling an optimality study of Monte Carlo simulation, a popular estimation method for reliability analysis, on real benchmark circuits. Our study shows that Monte Carlo simulation with a small set of random vectors generally has a high fidelity for the computation of full-chip fault rates and the criticality of single gates. While we focus on reliability analysis, RALF can also be used to efficiently locate random pattern resistant faults. This can be used to identify where methods other than random simulation should be used for accurate criticality calculations and where to enhance the testability of a circuit.

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Cited By

Jing NLee JFeng ZHe WMao ZHe L(2013)SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithmsACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2390191.239020418:1(1-18)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390204
Jing NLee JHe WMao ZHe LPhillips JHu AGraeb H(2011)Mitigating FPGA interconnect soft errors by in-place LUT inversionProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132458(582-586)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132458

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Published In

cover image ACM Conferences

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Jing NLee JFeng ZHe WMao ZHe L(2013)SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithmsACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2390191.239020418:1(1-18)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390204
Jing NLee JHe WMao ZHe LPhillips JHu AGraeb H(2011)Mitigating FPGA interconnect soft errors by in-place LUT inversionProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132458(582-586)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132458

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