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KL-cuts: a new approach for logic synthesis targeting multiple output blocks

Published: 08 March 2010 Publication History

Abstract

This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.

References

[1]
Ling, A. C., Zhu, J., "Scalable Synthesis and Clustering Techniques Using Decision Diagrams", IEEE Trans. on CAD. 2008.
[2]
Mishchenko, A., Brayton, R., "Scalable Logic Synthesis using a Simple Circuit Structure", Int'l Workshop on Logic & Synthesis, 2006. http://www.eecs.berkeley.edu/~alanmi/publications/2006/iwls06_sls.pdf
[3]
Cong J., Wu, C., Ding, Y., "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution", Int'l Symp. on FPGA, 1999.
[4]
Pan, P., Lin C., "A New Retiming-based Technology Mapping Algorithm for LUT-based FPGAs", Int'l Symp. on FPGA, 1998.
[5]
Mishchenko, A., Chatterjee, S., Brayton, R., "DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis", Design Automation Conference, 2006.
[6]
Mishchenko, A., Brayton, R., Chatterjee, S., "Boolean Factoring and Decomposition of Logic Networks", Int'l Conf. on CAD, 2008.
[7]
Chatterjee, S., Mishchenko, A. and Brayton, R., "Factor Cuts", Int'l Conf. on CAD, 2006.
[8]
Werber, J., Rautenbach, D., Szegedy, C., "Timing Optimization by Restructuring Long Combinatorial Paths", Int'l Conf. on CAD, 2007.
[9]
Rosiello, A. P. E., Ferrandi, F., Pandini, D., Sciuto, D., "A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis", IEEE Comp. Soc. Annual Symp. on VLSI, 2007.
[10]
Mishchenko, A., Chatterjee, S., Brayton, R., "Improvements to Technology Mapping for LUT-Based FPGAs", Int'l Symp. on FPGA, 2006.
[11]
Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification". http://www.eecs.berkeley.edu/~alanmi/abc
[12]
Xilinx, "Achieving Higher System Performance with the Virtex-5 Family of FPGAs", White Paper, 2006. http://www.xilinx.com/
[13]
Altera, "Improving FPGA Performance and Area Using an Adaptive Logic Module", White Paper, 2004. http://www.altera.com/
[14]
Mishchenko, A., Brayton, R., Jiang, J. H. R., Jang, S., "Scalable Don't-Care-Based Logic Optimization and Resynthesis", Int'l Symp. on FPGA, 2009.

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Published In

cover image ACM Conferences
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
March 2010
1868 pages
ISBN:9783981080162

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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Author Tags

  1. AIG
  2. cut enumeration
  3. technology mapping

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  • Research-article

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DATE '10
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '10: Design, Automation and Test in Europe
March 8 - 12, 2010
Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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DATE '25
Design, Automation and Test in Europe
March 31 - April 2, 2025
Lyon , France

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  • (2019)Partition and PropagateProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317878(1-6)Online publication date: 2-Jun-2019
  • (2018)BLASYSProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196001(1-6)Online publication date: 24-Jun-2018
  • (2018)Towards a VLSI Design Flow Based on Logic Computation and Signal DistributionProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3177557(58-59)Online publication date: 25-Mar-2018
  • (2017)Boolean Decomposition for AIG OptimizationProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060420(143-148)Online publication date: 10-May-2017
  • (2014)TACUEProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593227(1-6)Online publication date: 1-Jun-2014

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