research-article

Enhancing design robustness with reliability-aware resynthesis and logic simulation

Authors:

Smita Krishnaswamy,

Stephen M. Plaza,

Igor L. Markov,

John P. HayesAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 149 - 154

Published: 05 November 2007 Publication History

Abstract

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29--40% with only 5--13% area overhead.

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Digital Library

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Cited By

Lu YZhou HMacii E(2013)Retiming for Soft Error Minimization Under Error-Latching Window ConstraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485530(1008-1013)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485530
Jing NLee JFeng ZHe WMao ZHe L(2013)SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithmsACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020418:1(1-18)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390204
Wu KMarculesc D(2013)A low-cost, systematic methodology for soft error robustness of logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218414521:2(367-379)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2184145
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Enhancing design robustness with reliability-aware resynthesis and logic simulation
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Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

Publisher

IEEE Press

Publication History

Published: 05 November 2007

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Lu YZhou HMacii E(2013)Retiming for Soft Error Minimization Under Error-Latching Window ConstraintsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485530(1008-1013)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485530
Jing NLee JFeng ZHe WMao ZHe L(2013)SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithmsACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020418:1(1-18)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390204
Wu KMarculesc D(2013)A low-cost, systematic methodology for soft error robustness of logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218414521:2(367-379)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2184145
Peng CDong CChen D(2011)SETmapProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950897(388-393)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950897
Luckenbill SLee JHu YMajumdar RHe LDe Micheli GAl-Hashimi BMueller WMacii E(2010)RALF: reliability analysis for logic faultsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871113(783-788)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871113
Wu KMarculescu DDe Micheli GAl-Hashimi BMueller WMacii E(2010)Clock skew scheduling for soft-error-tolerant sequential circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871100(717-722)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871100
Marr BGeorge JDegnan BAnderson DHasler P(2010)Error immune logic for low-power probabilistic computingVLSI Design10.1155/2010/4603122010(1-9)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/460312
Jose MHu YMajumdar RHe LSapatnekar S(2010)Rewiring for robustnessProceedings of the 47th Design Automation Conference10.1145/1837274.1837391(469-474)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837391
He XAbdollahi ABahar RLombardi FAtienza DBrunvand E(2010)Cost aware fault tolerant logic synthesis in presence of soft errorsProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785518(151-154)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785518
Alves NNepal KDworak JBahar RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Detecting errors using multi-cycle invariance informationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874815(791-796)Online publication date: 20-Apr-2009
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