research-article

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors

Authors:

Sivaram Gopalakrishnan,

M. Brandon Meredith,

Florian EnescuAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 143 - 148

Published: 05 November 2007 Publication History

Abstract

Polynomial computations over fixed-size bit-vectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. However, fixed-size (m) bit-vector arithmetic is polynomial algebra over the finite integer ring Z₂m, which is a non-unique factorization domain (non-UFD). While non-UFDs provide an extra freedom to search for decompositions, they complicate polynomial manipulation as traditional division-based algorithms are inapplicable.

This paper presents new mathematical concepts for polynomial decomposition over Z₂m, for RTL synthesis over fixed-size m-bit vectors. Given a polynomial, we identify a specific set of linear expressions and compute the Gröbner bases of their ideal (over non-UFD Z₂m) using syzygies. This basis serves as good building-blocks for the given computation. A decomposition is identified by subsequent Gröbner basis reduction. Experimental results demonstrate significant area savings due to our approach, as compared against contemporary datapath synthesis techniques.

References

[1]

V. J. Mathews and G. L. Sicuranza, Polynomial Signal Processing, Wiley-Interscience, 2000.

[2]

A. Peymandoust and G. DeMicheli, "Application of Symbolic Computer Algebra in High-Level Data-Flow Synthesis", IEEE Trans. CAD, vol. 22, pp. 1154--11656, 2003.

Digital Library

[3]

J. Smith and G. DeMicheli, "Polynomial circuit models for component matching in high-level synthesis", IEEE Trans. VLSI, vol. 9, 2001.

Digital Library

[4]

K. Kum and W. Sung, "Word-length optimization for high-level synthesis of DSP systems", in Intl. workshop Signal Processing Systems, SIPS, 1998.

[5]

G. Constantinides, P. Cheung, and W. Luk, "Synthesis of saturation arithmetic architectures", ACM Trans. Des. Auto, pp. 334--354, July 2003.

Digital Library

[6]

J. Krumm, "Savitzky-Golay Filters for 2D Images", Available at http://homepages.inf.ed.ac.uk/rbf/CVon-line/LOCAL_COPIES/KRUMM1/SavGol.htm.

[7]

A. Hosangadi, F. Fallah, and R. Kastner, "Factoring and eliminating common subexpressions in polynomial expressions", in ICCAD, pp. 169--174, 2004.

Digital Library

[8]

A. Hosangadi, F. Fallah, and R. Kastner, "Optimizing polynomial expressions by algebraic factorization and common subexpression elimination", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 2012--2022, Oct 2006.

Digital Library

[9]

JuanCSE, "Extensible, programmable and reconfigurable embedded systems group", Available at http://express.ece.ucsb.edu/suif/cse.html.

[10]

W. Adams and P. Loustaunau, An Introduction to Gröbner Bases, American Mathematical Society, 1994.

[11]

J. Smith and G. DeMicheli, "Polynomial methods for component maching and verification", in In Proc. ICCAD, 1998.

Digital Library

[12]

J. Smith and G. DeMicheli, "Polynomial methods for allocating complex components", in Proc. DATE, 1999.

Digital Library

[13]

B. Buchberger, Ein Algorithmus zum Auffinden der Basiselemente des Restklassenringes nach einem nulldimensionalen Polynomideal, PhD thesis, Philosophiesche Fakultat an der Leopold-Franzens-Universitat, Austria, 1965.

[14]

B. Buchberger, "A Theoretical Basis for Reduction of Polynomials to Canonical Forms", ACM SIG-SAM Bulletin, vol. 10, pp. 19--29, 1976.

Digital Library

[15]

B. Buchberger, "Some Properties of Grobner Bases for Polynomial Ideals", ACM SIG-SAM Bulletin, 1976.

Digital Library

[16]

A. Hosangadi, F. Fallah, and R. Kastner, "Energy Efficient Hardware Synthesis of Polynomial Expressions", in Int'l. Conf. on VLSI Design, pp. pp. 653--658, 2005.

Digital Library

[17]

A. K. Verma and P. Ienne, "Improved use of the Carry-save Representation for the Synthesis of Complex Arithmetic Circuits", in Proceedings of the International Conference on Computer Aided Design, 2004.

Digital Library

[18]

Arvind and X. Shen, "Using term rewriting systems to design and verify processors", IEEE Micro, vol. 19, pp. 36--46, 1998.

Digital Library

[19]

A. K. Verma and P. Ienne, "Towards the Automatic Exploration of Arithmetic-Circuit Architectures", in Design Automation Conf., pp. 445--450, 2006.

Digital Library

[20]

J. Grabmeier, E. Kaltofen, and V. Weispfenning, Computer Algebra Handbook, Springer-Verlag, 2003.

Digital Library

[21]

C.-Y. Huang and K.-T. Cheng, "Using Word-Level ATPG and Modular Arithmetic Constraint Solving Techniques for Assertion Property Checking", IEEE Trans. CAD, vol. 20, pp. 381--391, 2001.

Digital Library

[22]

N. Shekhar, P. Kalla, F. Enescu, and S. Gopalakrishnan, "Equivalence Verification of Polynomial Datapaths with Fixed-Size Bit-Vectors using Finite Ring Algebra", in Intl. Conf. on Computer-Aided Design, ICCAD, 2005.

Digital Library

[23]

S. Gopalakrishnan, P. Kalla, and F. Enescu, "Optimization of arithmetic datapaths with finite word-length operands", in Proc. Asia-South Pacific Design Automation Conf., pp. 511--516, 2007.

Digital Library

[24]

R. J. B. T. Allenby, Rings, Fields, and Groups: An Introduction to Abstract Algebra., E. J. Arnold, 1983.

[25]

T. Becker and V. Weispfenning, Grobner Bases: A Computational Approach to Commutative Algebra, Springer-Verlag, 1993.

Digital Library

[26]

D. Cox, J. Little, and D. O'Shea, Ideals, Varieties and Algorithms, Springer-Verlag, 1997.

Digital Library

[27]

M. Clegg, J. Edmonds, and R. Impagliazzo, "Using the Grobner basis algorithm to find proofs of unsatisfiability", in ACM Symp. on Theory of Computation, pp. 174--183, 1996.

Digital Library

[28]

C. Condrat and P. Kalla, "A Groebner Basis Approach to CNF formulae Preprocessing", in TACAS, 2007.

Digital Library

[29]

M. Y. Vardi and Q. Tran, "Groebners Bases Computation in Boolean Rings for Symbolic Model Checking", in IASTED, 2007.

Digital Library

[30]

H. M. Moller, "On the construction of Gröbner bases using syzygies", J. Symb. Comp., vol. 6, pp. 345--359, 1988.

Digital Library

[31]

E. Carlini, "Reducing the number of variables of a polynomial", in Algebraic Geometry and Geometric Modeling, 2004.

[32]

"CPLEX Reference Manual, ILOG", 1999.

[33]

Maple, ", http://www.maplesoft.com.

[34]

M. R. Guthaus and et al., "Mibench: A Free, Commercially Representative Embedded Benchmark Suite", in IEEE 4th Annual Workshop on Workload Characterization, Dec 2001.

Digital Library

Cited By

Jain AMaskell DFahmy SFanucci LTeich J(2016)Throughput oriented FPGA overlays using DSP blocksProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972187(1628-1633)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972187
Haedicke FAlizadeh BFey GFujita MDrechsler RScheffer LPhillips JHu A(2010)Polynomial datapath optimization using constraint solving and formal modellingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133589(756-761)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133589
Alizadeh BFujita M(2010)Modular datapath optimization and verification based on modular-HEDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.205927129:9(1422-1435)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2059271
Show More Cited By

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
1. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis

Recommendations

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, ...
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96: Proceedings of the 9th international symposium on System synthesis

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
ICCD '05: Proceedings of the 2005 International Conference on Computer Design

This paper addresses the problem of equivalence veri fication of high-level/RTL descriptions. The focus is on datapath-oriented designs that implement univariate polynomial computations over fixed-size bit-vectors. When the size (m) of the entire ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

Publisher

IEEE Press

Publication History

Published: 05 November 2007

Check for updates

Qualifiers

Research-article

Conference

ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

Acceptance Rates

ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
109
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 06 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Jain AMaskell DFahmy SFanucci LTeich J(2016)Throughput oriented FPGA overlays using DSP blocksProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972187(1628-1633)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972187
Haedicke FAlizadeh BFey GFujita MDrechsler RScheffer LPhillips JHu A(2010)Polynomial datapath optimization using constraint solving and formal modellingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133589(756-761)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133589
Alizadeh BFujita M(2010)Modular datapath optimization and verification based on modular-HEDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.205927129:9(1422-1435)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2059271
Alizadeh BFujita MRoychowdhury J(2009)Improved heuristics for finite word-length polynomial datapath optimizationProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687536(739-744)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687536
Sarbishei OAlizadeh BFujita M(2009)Polynomial datapath optimization using partitioning and compensation heuristicsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630151(931-936)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630151

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten