research-article

Polynomial circuit models for component matching in high-level synthesis

Authors:

James Smith,

Giovanni De MicheliAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 9, Issue 6

Pages 783 - 800

https://doi.org/10.1109/92.974892

Published: 01 December 2001 Publication History

Abstract

Design reuse requires engineers to determine whether or not an existing block implements desired functionality. If a common high-level circuit model is used to represent components that are described at multiple levels of abstraction, comparisons between circuit specifications and a library of potential implementations can be performed accurately and quickly. A mechanism is presented for compactly specifying circuit functionality as polynomials at the word level. Polynomials can be used to represent circuits that are described at the bit level or arithmetically. Furthermore, in representing components as polynomials, differences in precision between potential implementations can be detected and quantified. We present a mechanism for constructing polynomial models for combinational and sequential circuits. Furthermore, we derive a means of approximating the functionality of nonpolynomial functions and determining a bound on the error of this approximation. These methods have been implemented in the POLYSYS synthesis tool and used to synthesize a JPEG encode block and infinite impulse response filter from a library of complex elements.

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Cited By

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Wei XDiao YLam TWu YNebel WAtienza D(2015)A universal macro block mapping scheme for arithmetic circuitsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757190(1629-1634)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757190
Pang YRadecka KZilic Z(2010)Optimization of imprecise circuits represented by Taylor series and real-valued polynomialsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204915429:8(1177-1190)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2049154
Gopalakrishnan SKalla PBenini LDe Micheli GAl-Hashimi BMueller W(2009)Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874969(1452-1457)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874969
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Index Terms

Polynomial circuit models for component matching in high-level synthesis
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 9, Issue 6

System Level Design

12/1/2001

261 pages

ISSN:1063-8210

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IEEE Educational Activities Department

United States

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Published: 01 December 2001

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Wei XDiao YLam TWu YNebel WAtienza D(2015)A universal macro block mapping scheme for arithmetic circuitsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757190(1629-1634)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757190
Pang YRadecka KZilic Z(2010)Optimization of imprecise circuits represented by Taylor series and real-valued polynomialsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204915429:8(1177-1190)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2049154
Gopalakrishnan SKalla PBenini LDe Micheli GAl-Hashimi BMueller W(2009)Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874969(1452-1457)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874969
Pang YRadecka KFix L(2008)Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transformProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391574(397-402)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391574
Gopalakrishnan SKalla PMeredith MEnescu FGielen G(2007)Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectorsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326103(143-148)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326103
Gopalakrishnan SKalla P(2007)Optimization of polynomial datapaths using finite ring algebraACM Transactions on Design Automation of Electronic Systems10.1145/1278349.127836212:4(49-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1278349.1278362
Gopalakrishnan SKalla PEnescu F(2007)Optimization of Arithmetic Datapaths with Finite Word-Length OperandsProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358037(511-516)Online publication date: 23-Jan-2007
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Radecka KZilic ZPileggi LKuehlmann A(2002)Specifying and verifying imprecise sequential datapaths by Arithmetic TransformsProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774591(128-131)Online publication date: 10-Nov-2002
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Peymandoust AMicheli GSimunic TAckland B(2002)Complex library mapping for embedded software using symbolic algebraProceedings of the 39th annual Design Automation Conference10.1145/513918.514003(325-330)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514003

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