Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1007/11596110_6guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Compiler optimizations with DSP-Specific semantic descriptions

Published: 25 July 2002 Publication History
  • Get Citation Alerts
  • Abstract

    Due to the specialized architecture and stream-based instruction set, traditional DSP compilers usually yield poor-quality object codes. Lack of an insight into the DSP architecture and the specific semantics of DSP applications, a compiler would have trouble selecting appropriate special instructions to exploit advanced hardware features. In order to extract optimal performance from DSPs, we propose a set of user-specified directives called Digital Signal Processing Interface (DSPI), which can facilitate code generation by relaying DSP specific semantics to compilers. We have implemented a prototype compiler based on the SPAM and SUIF compiler toolkits and integrated the DSPI into the prototype compiler. The compiler is currently targeted to TI's TMS320C6X DSP and will be extended to a retargetable compiler toolkit for embedded systems and System-on-a-Chip (SoC) platforms. Preliminary experimental results show that by incorporating DSPI directives significant performance improvements can be achieved in several DSP applications.

    References

    [1]
    Eduard Ayguade, Xavier Martorell, Jesus Labarta, Marc Gonzalez, and Nacho Navarro. Exploiting multiple levels of parallelism in openmp: A case study. In International Conference on Parallel Processing, pages 172-180, 1999.
    [2]
    D. Batten, S. Jinturkar, J. Glossner, M. Schulte, and P. D'Arcy. A new approach to dsp intrinsic functions. In Proceedings of the Hawaii International Conference on System Sciences, pages 908-918, January 2000.
    [3]
    D. Batten, S. Jinturkar, J. Glossner, M. Schulte, R. Peri, and P. D'Arcy. Interaction between optimizations and a new type of dsp intrinsic function. In Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT'99), November 1999.
    [4]
    Z. Bozkus, A. Choudhary, G. Fox, T. Haupt, and S. Ranka. Fortran 90d/hpf compiler for distributed memory mimd computers: design, implementation and performance results. In Proceedings of Supercomputing '93, pages 351-360, November 1993.
    [5]
    R. G. Chang, T. R. Chuang, and Jenq-Kuen Lee. Efficient support of parallel sparse computation for array intrinsic functions of fortran 90. In Proceedings of ACM International Conference on Supercomputing, July 1998.
    [6]
    Rong-Guey Chang, Jia-Shing Li, Tyng-Ruey Chuang, and Jenq Kuen Lee. Probabilistic inference schemes for sparsity structures of fortran 90 array intrinsics. In Proceedings of the 2001 International Conference on Parallel Processing, September 2001.
    [7]
    D. Chen, W. Zhao, and H. Ru. Design and implementation issues of intrinsic functions for embedded dsp processors. In Proceedings of the ACM SIGPLAN International Conference on Signal Processing Applications and Technology (ICSPAT'97), pages 505-509, September 1997.
    [8]
    Naji Ghazal, Richard Newton, and Jan Rabaey. Predicting performance potential of modern dsps. In Proceedings of IEEE/ACM Design Automation Conference (DAC), June 2000.
    [9]
    SPAM Research Group. SPAM Compiler User's Manual, September 1997. http://www.ee.princeton.edu/spam/.
    [10]
    Stanford Compiler Group. The SUIF Library, 1994. http://suif.stanford.edu/suif/suif1/docs/suif toc.html.
    [11]
    G. Hadjiyiannis, S. Hanono, and S. Devadas. Isdl: An instruction set description language for retargetability. In Proceedings of ACM/IEEE Design Automation Conference, October 1997.
    [12]
    Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil Dutt, and Alex Nicolau. Expression: A language for architecture exploration through compiler/ simulator retargetability. In Proceedings of Design, Automation, and Test in Europe conference (DATE), 1999.
    [13]
    Gwan-Hwan Hwang, Jenq Kuen Lee, and Dz-Ching Ju. Integrating automatic data alignment and array operation synthesis to optimize data parallel programs. In Proceedings of the 10th International Workshop on Languages and Compilers for Parallel Computing (LCPC'97), Augest 1997.
    [14]
    Gwan-Hwan Hwang, Jenq Kuen Lee, and Roy Dz-Ching Ju. A function-composition approach to synthesize fortran 90 array operations. Journal of Parallel and Distributed Computing, 54:1-47, 1998.
    [15]
    Yuan-Shin Hwang, Peng-Sheng Chen, Jenq-Kuen Lee, and Roy Ju. Probabilistic points-to analysis. In Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing (LCPC'01), August 2001.
    [16]
    Texas Instruments Incorporated. TMS320C62x/C67x CPU and Instruction Set. Texas Instuments Incorporated, 1998. http://www.ti.com/sc/psheets/spru189d/spru189d.pdf.
    [17]
    M. Jersak and M. Willems. Fixed-point extended c compiler allows more efficient high-level programming of fixed-point dsps. In Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT'98), October 1998.
    [18]
    J. Glossner, D. Routenberg, E. Hokenek, M. Moudgill, M. Schulte, P. Balzola, and S. Vassiliadis. Towards a very high bandwidth wireless handheld device. Technical report, Sandbridge Technologies, Inc., 2001. White Paper.
    [19]
    B. Krepp. Dsp-oriented extension to ansi c. In Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT'97), pages 658-664, 1997.
    [20]
    Ashutosh K. Kulkarni and Aditya Dube. Benchmarking code generation methodologies for programmable digital signal processors. April 1997.
    [21]
    K. Leary and W. Waddington. Dsp/c: a standard high level language for dsp aad numeric processing. In Proceedings of the International Conference on Acoustic, Speech, and Signal Processing, pages 1065-1068, 1990.
    [22]
    Chingren Lee, Jenq Kuen Lee, TingTing Hwang, and Shi-Chun Tsai. Compiler optimization on instruction scheduling for low power. In Proceedings of the 13th International Symposium on System Synthesis, pages 55-60, September 2000.
    [23]
    Yi-Ping You, Ching-Ren Lee, Jenq-Kuen Lee, and Wei-Kuan Shih. Real-time task scheduling for dynamically variable voltage processors. In Proceedings of IEEE Workshop on Power Management for Real-Time and Embedded Systems, May 2001.
    [24]
    V. Zivojnovic, S. Pees, and H. Meyr. Lisa - machine description language and generic machine model for hw/sw co-design. In Proceedings of IEEE Workshop on VLSI Signal Processing, October 1996.
    [25]
    V. Zivojnovic, J.M. Velarde, C. Schlager, and H. Meyr. Dspstone, a dsp-oriented benchmarking methodology - final report. Technical report, Aachen University, Germany, August 1994. Technical Report.

    Cited By

    View all
    • (2012)Extendable pattern-oriented optimization directivesACM Transactions on Architecture and Code Optimization (TACO)10.1145/2355585.23555879:3(1-37)Online publication date: 5-Oct-2012
    • (2011)Extendable pattern-oriented optimization directivesProceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization10.5555/2190025.2190058(107-118)Online publication date: 2-Apr-2011
    • (2003)Compiler support for speculative multithreading architecture with probabilistic points-to analysisACM SIGPLAN Notices10.1145/966049.78150238:10(25-36)Online publication date: 11-Jun-2003
    • Show More Cited By

    Index Terms

    1. Compiler optimizations with DSP-Specific semantic descriptions
      Index terms have been assigned to the content through auto-classification.

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image Guide Proceedings
      LCPC'02: Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
      July 2002
      376 pages
      ISBN:3540307818
      • Editors:
      • Bill Pugh,
      • Chau-Wen Tseng

      Sponsors

      • UMIACS: U of MD Inst for Advanced Comp Studies

      Publisher

      Springer-Verlag

      Berlin, Heidelberg

      Publication History

      Published: 25 July 2002

      Qualifiers

      • Article

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 10 Aug 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2012)Extendable pattern-oriented optimization directivesACM Transactions on Architecture and Code Optimization (TACO)10.1145/2355585.23555879:3(1-37)Online publication date: 5-Oct-2012
      • (2011)Extendable pattern-oriented optimization directivesProceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization10.5555/2190025.2190058(107-118)Online publication date: 2-Apr-2011
      • (2003)Compiler support for speculative multithreading architecture with probabilistic points-to analysisACM SIGPLAN Notices10.1145/966049.78150238:10(25-36)Online publication date: 11-Jun-2003
      • (2003)Compiler support for speculative multithreading architecture with probabilistic points-to analysisProceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming10.1145/781498.781502(25-36)Online publication date: 11-Jun-2003

      View Options

      View options

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media