Article

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors

Authors:

Matteo Perotti,

Giuseppe Tagliavini,

Luca Bertaccini,

Luca BeniniAuthors Info & Claims

Embedded Computer Systems: Architectures, Modeling, and Simulation: 21st International Conference, SAMOS 2021, Virtual Event, July 4–8, 2021, Proceedings

Pages 16 - 32

https://doi.org/10.1007/978-3-031-04580-6_2

Published: 04 July 2021 Publication History

Abstract

Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable. Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints. We propose RVfplib, the first ISA-optimized open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59% smaller and 2

\times

faster than the GCC emulation library, on average. On benchmark programs, code size reduction is 39%, and performance boost 1.5

\times

. RVfplib is 5.3% smaller than the leading closed-source RISC-V commercial library.

References

[1]

Arm Keil - fplib. https://www.keil.com/support/man/docs/armlib/armlib_chr1358938941317.html

[2]

Bertaccini, L., Perotti, M., Mach, S., Schiavone, P.D., Zaruba, F., Benini, L.: Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores. In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2021).

[3]

Code size reduction official sub-committee. https://lists.riscv.org/g/tech-code-size

[4]

Embench benchmark suite. https://github.com/embench/embench-iot

[5]

FLIP library. http://flip.gforge.inria.fr/

[6]

Gautschi, M., et al.: Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(10), 2700–2713 (2017).

[7]

GigaDevice Semiconductor Inc.: GD32VF103 RISC-V 32-bit MCU User Manual, Revision 1.2, October 2019

[8]

Gottscho M, Alam I, Schoeny C, Dolecek L, and Gupta P Low-cost memory fault tolerance for IoT devices ACM Trans. Embed. Comput. Syst. 2017 16 5s 1-25

[9]

libgcc - Arm floating-point support. https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/arm/ieee754-sf.S

[10]

libgcc library. https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html

[11]

OpenHW Group CV32E40P user manual. https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/index.html

[12]

Perotti, M., et al.: HW/SW approaches for RISC-V code size reduction (2020).

[13]

Pimentel, J.J., Bohnenstiehl, B., Baas, B.M.: Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(1), 100–113 (2016)

[14]

Qfplib library. https://www.quinapalus.com/qfplib.html

[15]

RISC-V - Arm comparison, Embench. https://riscv.org/wp-content/uploads/2019/12/12.10-12.50a-Code-Size-of-RISC-V-versus-ARM-using-the-Embench%E2%84%A2-0.5-Benchmark-Suite-What-is-the-Cost-of-ISA-Simplicity.pdf

[16]

RISC-V Bit-Manipulation extension draft. https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

[17]

SEGGER emFloat. https://www.segger.com/products/development-tools/runtime-library/technology/floating-point-library/

[18]

SEGGER wiki. https://wiki.segger.com/SEGGER_Floating-Point_Library

[19]

SoftFloat. http://www.jhauser.us/arithmetic/SoftFloat.html

[20]

TestFloat. http://www.jhauser.us/arithmetic/TestFloat.html

Index Terms

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors

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Information & Contributors

Information

Published In

cover image Guide Proceedings

Embedded Computer Systems: Architectures, Modeling, and Simulation: 21st International Conference, SAMOS 2021, Virtual Event, July 4–8, 2021, Proceedings

Jul 2021

527 pages

ISBN:978-3-031-04579-0

DOI:10.1007/978-3-031-04580-6

Editors:
Alex Orailoglu
University of California, San Diego, La Jolla, CA, USA
,
Matthias Jung
Fraunhofer IESE, Kaiserslautern, Germany
,
Marc Reichenbach
Brandenburg University of Technology, Cottbus, Germany

© Springer Nature Switzerland AG 2022.

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 04 July 2021

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