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- research-articleJanuary 2025
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-core Computing Clusters for Reliable Processing in Space
ACM Transactions on Cyber-Physical Systems (TCPS), Volume 9, Issue 1Article No.: 8, Pages 1–29https://doi.org/10.1145/3635161Space Cyber-Physical Systems such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing ...
- posterDecember 2024
Poster: Marian: An Open Source RISC-V Processor with Zvk Vector Cryptography Extensions
CCS '24: Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications SecurityPages 4931–4933https://doi.org/10.1145/3658644.3691394The RISC-V Vector Cryptography Extensions (Zvk) were ratified in 2023 and integrated into the main ISA manuals in 2024. These extensions support high-speed symmetric cryptography (AES, SHA2, SM3, SM4) operating on the vector register file and offer ...
- ArticleNovember 2024
Formal Verification of RISC-V Processor Chisel Designs
Dependable Software Engineering. Theories, Tools, and ApplicationsPages 142–160https://doi.org/10.1007/978-981-96-0602-3_8AbstractChisel is an open-source high-level hardware construction language embedded in Scala to facilitate parameterizable, reusable circuit design generators. It is becoming increasingly popular and has been used to design many RISC-V processor variants. ...
- research-articleNovember 2024
Energy-efficient instruction compression with programmable dictionaries: Energy-efficient instruction compression...
Design Automation for Embedded Systems (DAES), Volume 28, Issue 3Pages 245–274https://doi.org/10.1007/s10617-024-09290-2AbstractTo improve the energy efficiency of computation, accelerators trade off performance and energy consumption for flexibility. Fixed-function accelerators reach high energy efficiency, but are inflexible. Adding programmability via an instruction set ...
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- research-articleNovember 2024
Deploying human activity recognition in embedded RISC-V processors: Deploying human activity recognition in embedded RISC-V processors
- Willian Analdo Nunes,
- Rafael Schild Reusch,
- Lucas Luza,
- Eduardo Bernardon,
- Angelo Elias Dal Zotto,
- Leonardo Rezende Juracy,
- Fernando Gehm Moraes
Design Automation for Embedded Systems (DAES), Volume 28, Issue 3Pages 187–217https://doi.org/10.1007/s10617-024-09288-wAbstractHuman Activity Recognition (HAR) is an important area of research due to its applications in health monitoring, elderly care, and personal fitness tracking. The challenge is deploying efficient and accurate HAR systems on resource-constrained and/...
- research-articleNovember 2024
RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb
Frontiers of Computer Science: Selected Publications from Chinese Universities (FCS), Volume 19, Issue 1https://doi.org/10.1007/s11704-023-3239-xAbstractThe rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field. To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple ...
- research-articleJanuary 2025
Lower the RISC: Designing optical-probing-attack-resistant cores
Microprocessors & Microsystems (MSYS), Volume 111, Issue Chttps://doi.org/10.1016/j.micpro.2024.105121AbstractRecently, a new Side-Channel Analysis (SCA)-based attack, namely the Optical Probing (OP) attack, has been shown to bypass the implemented protection mechanisms on the chip, allowing unauthorized access to confidential information such as stored ...
- research-articleNovember 2024
TaPaFuzz: Hardware-accelerated RISC-V bare-metal firmware fuzzing using rapid job launches
Journal of Systems Architecture: the EUROMICRO Journal (JOSA), Volume 156, Issue Chttps://doi.org/10.1016/j.sysarc.2024.103288AbstractFuzz testing serves as a key technique in software security aimed at identifying unexpected program behaviors by repeatedly executing the target program with auto-generated random inputs. Testing is integral to IoT device security but is hampered ...
- research-articleOctober 2024JUST ACCEPTED
Conflict Management in Vector Register Files
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3702002The instruction set architecture (ISA) of vector processors operates on vectors stored in the vector register file (VRF) which needs to handle several concurrent accesses by functional units (FUs) with multiple ports. When the vector processor is running ...
- research-articleOctober 2024
MiniJava on RISC-V: A Game of Global Compilers Domination
JENSFEST '24: Proceedings of the Workshop Dedicated to Jens Palsberg on the Occasion of His 60th BirthdayPages 21–29https://doi.org/10.1145/3694848.3694854Over two decades have passed since the first publication of Modern Compiler Implementation by Andrew Appel, with its second edition revised by Jens Palsberg. This textbook remains an essential guide for students, hobbyists, and researchers navigating the ...
- research-articleOctober 2024
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 17, Issue 4Article No.: 54, Pages 1–22https://doi.org/10.1145/3653459Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for ...
- research-articleOctober 2024
SLOPE: Safety LOg PEripherals implementation and software drivers for a safe RISC-V microcontroller unit
Microprocessors & Microsystems (MSYS), Volume 110, Issue Chttps://doi.org/10.1016/j.micpro.2024.105103AbstractThe focus of this manuscript is related to the main safety issues regarding a mixed criticality system running multiple concurrent tasks. Our concerns are related to the guarantee of Freedom of Interference between concurrent partitions, and to ...
- research-articleSeptember 2024
- research-articleJanuary 2025
A Review of Big Data Applications Based on RISC-V
ADMIT '24: Proceedings of the 2024 3rd International Conference on Algorithms, Data Mining, and Information TechnologyPages 316–320https://doi.org/10.1145/3701100.3701165With the rapid development of big data technology, there is an increasing demand for underlying computing architectures. RISC-V, as an open-source instruction set architecture, has shown tremendous potential and advantage in the field of big data due to ...
- research-articleSeptember 2024
Offloading Datacenter Jobs to RISC-V Hardware for Improved Performance and Power Efficiency
SYSTOR '24: Proceedings of the 17th ACM International Systems and Storage ConferencePages 39–52https://doi.org/10.1145/3688351.3689152The end of Moore's Law has brought significant changes in the architecture of servers used in data centers, increasingly incorporating new ISAs beyond x86-64 as well as diverse accelerators. Further, single-board computers have become increasingly ...
- ArticleSeptember 2024
ReminISCence: Trusted Monitoring Against Privileged Preemption Side-Channel Attacks
AbstractTrusted Execution Environments (TEEs) have long served as a prominent security measure for ensuring isolation and data privacy in cloud environments. However, their security foundations face challenges from numerous side-channel threats, ...
- research-articleDecember 2024
A Quick Response Method for Higher-priority Interrupts Based on the RISC-V Architecture
ICCSIE '24: Proceedings of the 2024 9th International Conference on Cyber Security and Information EngineeringPages 369–375https://doi.org/10.1145/3689236.3689249Abstract: To accelerate the quick response of CPUs in real-time application fields for higher-priority interrupts, this paper presents a quick response method for higher-priority interrupts based on RISC-V. After the CPU responds to an interrupt and ...
- research-articleSeptember 2024JUST ACCEPTED
Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading
- Maicol Ciani,
- Emanuele Parisi,
- Alberto Musa,
- Francesco Barchi,
- Andrea Bartolini,
- Ari Kulmala,
- Rafail Psiakis,
- Angelo Garofalo,
- Andrea Acquaviva,
- Rossi Davide
ACM Transactions on Embedded Computing Systems (TECS), Just Accepted https://doi.org/10.1145/3690823The rapid advancement and exploration of open-hardware RISC-V platforms are catalyzing substantial changes across critical sectors, including autonomous vehicles, smart-city infrastructure, and medical devices. Within this technological evolution, ...
- research-articleSeptember 2024
Count overflow and privilege mode filtering extension implementation on a RISC-V on-board processor
- Andrea Fernández Gallego,
- Miguel Jiménez Arribas,
- Iván Gamino del Río,
- Agustín Martínez Hellín,
- Manuel Prieto Mateo,
- Óscar Rodríguez Polo,
- Antonio da Silva,
- Pablo Parra,
- Sebastián Sánchez
Microprocessors & Microsystems (MSYS), Volume 109, Issue Chttps://doi.org/10.1016/j.micpro.2024.105084AbstractRISC-V is a computer architecture that has recently attracted considerable attention due to its advantageous qualities: it is an open instruction set, based on reduced and simple instructions. For this reason it has become an appealing choice ...