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Offloading Datacenter Jobs to RISC-V Hardware for Improved Performance and Power Efficiency

Published: 16 September 2024 Publication History

Abstract

The end of Moore's Law has brought significant changes in the architecture of servers used in data centers, increasingly incorporating new ISAs beyond x86-64 as well as diverse accelerators. Further, single-board computers have become increasingly efficient and can run certain Linux applications at significantly lower equipment and energy costs compared to traditional servers. Past research has demonstrated that offloading applications at runtime from x86-based servers to ARM-based single-board computers can result in increases in throughput and energy efficiency. The RISC-V architecture has recently gained significant commercial interest, and OS-capable single-board computers with RISC-V cores are increasingly available at the commodity scale.
In this paper we propose a system that offloads jobs from an x86 server to a RISC-V single-board computer at runtime, with the goals of improving job throughput and energy saved. Towards this, we port the Popcorn Linux multi-ISA toolchain and runtime framework to RISC-V, enabling the live migration of applications between an x86 Xeon server and a SiFive HiFive RISC-V board. We further propose a scheduling policy, Lowest Slowdown First (LSF) that drives the offloading of long-running and stateful datacenter background jobs from the server to the board, to alleviate workload congestion on the server. LSF's policy relies on monitoring jobs' performance on the server, predicting the slowdown they would suffer if running on the board, and migrating the jobs with the lowest estimated slowdown. Our evaluation shows that LSF yields up to 20% increase in throughput while also gaining 16% more energy efficiency for compute-intensive workloads.

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cover image ACM Conferences
SYSTOR '24: Proceedings of the 17th ACM International Systems and Storage Conference
September 2024
212 pages
ISBN:9798400711817
DOI:10.1145/3688351
This work is licensed under a Creative Commons Attribution International 4.0 License.

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Published: 16 September 2024

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  1. RISC-V
  2. execution migration
  3. heterogeneous ISA
  4. x86

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SYSTOR '24 Paper Acceptance Rate 14 of 38 submissions, 37%;
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