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View all- Hu WShi WTang ZLi M(1998)A lock-based cache coherence protocol for scope consistencyJournal of Computer Science and Technology10.1007/BF0294659913:2(97-109)Online publication date: 1-Mar-1998
A framework of memory consistency models
Authors: 
Weiwu Hu, Weisong Shi, Zhimin TangAuthors Info & Claims
Weiwu Hu, Weisong Shi, Zhimin TangAuthors Info & ClaimsPages 110 - 124
Abstract
Previous descriptions of memory consistency models in shared-memory multiprocessor systems are mainly expressed as constraints on the memory access event ordering and hence are hardware-centric. This paper presents a framework of memory consistency models which describes the memory consistency model on the behavior level. Based on the understanding that the behavior of an execution is determined by the execution order of conflicting accesses, a memory consistency model is defined as an interprocessor synchronization mechanism which orders the execution of operations from different processors. Synchronization order of an execution under certain consistency model is also defined. The synchronization order, together with the program order, determines the behavior of an execution.
This paper also presents criteria for correct program and correct implementation of consistency models. Regarding an implementation of a consistency model as certain memory event ordering constraints, this paper provides a method to prove the correctness of consistency model implementations, and the correctness of the lock-based cache coherence protocol is proved with this method.
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© Science Press, Beijing China and Allerton Press Inc. 1998.
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Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 22 March 2023
Revision received: 18 December 1997
Received: 27 October 1997
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