article

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Authors:

Majid Moghaddam,

Somayeh Timarchi,

Mohammad Hossein Moaiyeri,

Mohammad EshghiAuthors Info & Claims

Circuits, Systems, and Signal Processing, Volume 35, Issue 5

Pages 1437 - 1455

https://doi.org/10.1007/s00034-015-0119-0

Published: 01 May 2016 Publication History

Abstract

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body---source voltage dynamically. Proper usage of low-threshold voltage (L-$$V_{\mathrm{t}}$$Vt) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power---delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.

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Cited By

Dahiya AMittal PRohilla R(2023)Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read PerformanceCircuits, Systems, and Signal Processing10.1007/s00034-023-02397-042:10(5799-5810)Online publication date: 23-May-2023
https://dl.acm.org/doi/10.1007/s00034-023-02397-0
Joy AKuruvilla J(2022)A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency AnalysisWireless Personal Communications: An International Journal10.1007/s11277-022-09865-x126:4(3305-3316)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1007/s11277-022-09865-x
Mohana chandrika OSiva kumar M(2022)Design and analysis of SRAM cell using reversible logic gates towards smart computingThe Journal of Supercomputing10.1007/s11227-021-03851-z78:2(2287-2306)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03851-z
Show More Cited By

Index Terms

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques
1. Hardware
  1. Hardware validation
  2. Very large scale integration design

Index terms have been assigned to the content through auto-classification.

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Published In

cover image Circuits, Systems, and Signal Processing

Circuits, Systems, and Signal Processing Volume 35, Issue 5

May 2016

357 pages

ISSN:0278-081X

Issue’s Table of Contents

Copyright © Copyright © 2016 Springer Science+Business Media New York.

Publisher

Birkhauser Boston Inc.

United States

Publication History

Published: 01 May 2016

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Cited By

Dahiya AMittal PRohilla R(2023)Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read PerformanceCircuits, Systems, and Signal Processing10.1007/s00034-023-02397-042:10(5799-5810)Online publication date: 23-May-2023
https://dl.acm.org/doi/10.1007/s00034-023-02397-0
Joy AKuruvilla J(2022)A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency AnalysisWireless Personal Communications: An International Journal10.1007/s11277-022-09865-x126:4(3305-3316)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1007/s11277-022-09865-x
Mohana chandrika OSiva kumar M(2022)Design and analysis of SRAM cell using reversible logic gates towards smart computingThe Journal of Supercomputing10.1007/s11227-021-03851-z78:2(2287-2306)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03851-z
Pal SBose SIslam A(2022)Design of SRAM cell for low power portable healthcare applicationsMicrosystem Technologies10.1007/s00542-020-04809-628:3(833-844)Online publication date: 1-Mar-2022
https://dl.acm.org/doi/10.1007/s00542-020-04809-6
Shakouri EEbrahimi BEslami NChahardori M(2021)Single-Ended 10T SRAM Cell with High Yield and Low Standby PowerCircuits, Systems, and Signal Processing10.1007/s00034-020-01636-y40:7(3479-3499)Online publication date: 1-Jul-2021
https://dl.acm.org/doi/10.1007/s00034-020-01636-y
Mishra JUpadhyay BMisra PGoswami M(2021)Design and Analysis of SRAM cell using Body Bias Controller for Low Power ApplicationsCircuits, Systems, and Signal Processing10.1007/s00034-020-01578-540:5(2135-2158)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1007/s00034-020-01578-5
Morsali MMoaiyeri M(2020)NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power DesignCircuits, Systems, and Signal Processing10.1007/s00034-019-01309-539:6(2841-2859)Online publication date: 1-Jun-2020
https://dl.acm.org/doi/10.1007/s00034-019-01309-5
Gavaskar KRagupathy UMalini V(2019)Proposed Design of 1 KB Memory Array Structure for Cache MemoriesWireless Personal Communications: An International Journal10.1007/s11277-019-06593-7109:2(823-847)Online publication date: 1-Nov-2019
https://dl.acm.org/doi/10.1007/s11277-019-06593-7
Gavaskar KRagupathy UMalini V(2019)Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded MemoriesWireless Personal Communications: An International Journal10.1007/s11277-019-06523-7108:4(2311-2339)Online publication date: 1-Oct-2019
https://dl.acm.org/doi/10.1007/s11277-019-06523-7
Sayyah Ensan SMoaiyeri MEbrahimi BHessabi SAfzali-Kusha A(2019)A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technologyJournal of Computational Electronics10.1007/s10825-019-01327-118:2(519-526)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10825-019-01327-1
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