research-article

CAP-W

Authors:

Masoud Daneshtalab,

Dan ZhaoAuthors Info & Claims

Microprocessors & Microsystems, Volume 52, Issue C

Pages 23 - 33

https://doi.org/10.1016/j.micpro.2017.05.014

Published: 01 July 2017 Publication History

Abstract

In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC architecture. However, congestion occurrence in wireless routers reduces the benefit of high-speed wireless links and significantly increases the network latency. Therefore, in this paper, a congestion-aware platform, named CAP-W, is introduced for wireless-based NoC in order to reduce congestion in the network and especially over wireless routers. The triple-layer platform of CAP-W is composed of mapping, migration, and routing layers. In order to minimize the congestion probability, the mapping layer is responsible for selecting the suitable free core as the first candidate, finding the suitable first task to be mapped onto the selected core, and allocating other tasks with respect to contiguity. Considering dynamic variation of application behaviors, the migration layer modifies the primary task mapping to improve congestion situation. Furthermore, the routing layer balances utilization of wired and wireless networks by separating short-distance and long-distance communications. Experimental results show meaningful gain in congestion control of wireless-based NoC compared to state-of-the-art works.

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Cited By

Mortazavi SAkbar RSafaei FRezaei A(2019)A fault-tolerant and congestion-aware architecture for wireless networks-on-chipWireless Networks10.1007/s11276-019-01962-325:6(3675-3687)Online publication date: 20-Jul-2019
https://dl.acm.org/doi/10.1007/s11276-019-01962-3
Yazdanpanah FAfsharmazayejani RAlaei MRezaei ADaneshtalab M(2019)An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chipThe Journal of Supercomputing10.1007/s11227-018-2617-x75:2(837-861)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s11227-018-2617-x

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cover image Microprocessors & Microsystems

Microprocessors & Microsystems Volume 52, Issue C

July 2017

556 pages

ISSN:0141-9331

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Copyright © Elsevier B.V.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 July 2017

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Cited By

Mortazavi SAkbar RSafaei FRezaei A(2019)A fault-tolerant and congestion-aware architecture for wireless networks-on-chipWireless Networks10.1007/s11276-019-01962-325:6(3675-3687)Online publication date: 20-Jul-2019
https://dl.acm.org/doi/10.1007/s11276-019-01962-3
Yazdanpanah FAfsharmazayejani RAlaei MRezaei ADaneshtalab M(2019)An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chipThe Journal of Supercomputing10.1007/s11227-018-2617-x75:2(837-861)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s11227-018-2617-x

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