article

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

Authors:

Pieter Van Der Wolf,

Ed DeprettereAuthors Info & Claims

Journal of VLSI Signal Processing Systems, Volume 29, Issue 3

Pages 197 - 207

https://doi.org/10.1023/A:1012231429554

Published: 01 November 2001 Publication History

Abstract

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.

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Digital Library

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Index Terms

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems

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Published In

cover image Journal of VLSI Signal Processing Systems

Journal of VLSI Signal Processing Systems Volume 29, Issue 3

Special issue on signal processing systems design and implementation

November 2001

106 pages

ISSN:0922-5773

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Copyright © Copyright © 2001 Kluwer Academic Publishers.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 November 2001

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Cited By

Vu HNours SPillement SStemmer RGrüttner K(2021)A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoCProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431418(17-22)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431418
Yang SLe Nours SMéndez Real MPillement S(2019)System-Level Modeling and Simulation of MPSoC Run-Time Management Using Execution Traces AnalysisEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_20(281-293)Online publication date: 7-Jul-2019
https://dl.acm.org/doi/10.1007/978-3-030-27562-4_20
Nours SPostula A(2018)A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources ConflictsJournal of Signal Processing Systems10.5555/3288382.328840590:12(1667-1685)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.5555/3288382.3288405
Javaid HYachide YShwe SBokhari HParameswaran S(2014)FALCONProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593138(1-6)Online publication date: 1-Jun-2014
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Majdoub TLe Nours SPasquier ONouvel F(2014)Performance evaluation of an automotive distributed architecture based on a high speed power line communication protocol using a transaction level modeling approachJournal of Real-Time Image Processing10.1007/s11554-013-0323-89:1(281-295)Online publication date: 1-Mar-2014
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Nurmi JKhan SSaastamoinen JHuusko JSoininen J(2013)Application Workload Modelling via Run-Time Performance StatisticsInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20130401014:2(1-35)Online publication date: 1-Apr-2013
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Barreteau ANours SPasquier O(2012)A state-based modeling approach for efficient performance evaluation of embedded system architectures at transaction levelJournal of Electrical and Computer Engineering10.1155/2012/5373272012(4-4)Online publication date: 1-Jan-2012
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Cope BCheung PLuk WHowes L(2011)A systematic design space exploration approach to customising multi-processor architecturesTransactions on High-Performance Embedded Architectures and Compilers IV10.5555/2172445.2172450(63-83)Online publication date: 1-Jan-2011
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Kreku JTiensyrjä KVanmeerbeeck GDe Micheli GAl-Hashimi BMueller WMacii E(2010)Automatic workload generation for system-level exploration based on modified GCC compilerProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871016(369-374)Online publication date: 8-Mar-2010
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