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Assessing Probabilistic Timing Constraints on System Performance

Authors:

Jian-Huei GuoAuthors Info & Claims

Design Automation for Embedded Systems, Volume 5, Issue 1

Pages 61 - 81

https://doi.org/10.1023/A:1008991500612

Published: 01 February 2000 Publication History

Abstract

We propose an algorithm for assessing probabilistic timing constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of such constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints.

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Cited By

Kim BKyung C(2018)Exploiting intellectual properties with imprecise design costs for system-on-chip synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.104332710:3(240-252)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2002.1043327
Ouyang JRaghavendra RMohan SZhang TXie YMueller FHenkel JParameswaran S(2009)CheckerCoreProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629421(175-184)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629395.1629421
Manolache SEles PPeng Z(2004)Schedulability analysis of applications with stochastic task execution timesACM Transactions on Embedded Computing Systems (TECS)10.1145/1027794.10277973:4(706-735)Online publication date: 1-Nov-2004
https://dl.acm.org/doi/10.1145/1027794.1027797

Assessing Probabilistic Timing Constraints on System Performance
1. Computer systems organization

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cover image Design Automation for Embedded Systems

Design Automation for Embedded Systems Volume 5, Issue 1

February 2000

108 pages

ISSN:0929-5585

Issue’s Table of Contents

Copyright © Copyright © 2000 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 February 2000

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Cited By

Kim BKyung C(2018)Exploiting intellectual properties with imprecise design costs for system-on-chip synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.104332710:3(240-252)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2002.1043327
Ouyang JRaghavendra RMohan SZhang TXie YMueller FHenkel JParameswaran S(2009)CheckerCoreProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629421(175-184)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629395.1629421
Manolache SEles PPeng Z(2004)Schedulability analysis of applications with stochastic task execution timesACM Transactions on Embedded Computing Systems (TECS)10.1145/1027794.10277973:4(706-735)Online publication date: 1-Nov-2004
https://dl.acm.org/doi/10.1145/1027794.1027797

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