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Post-Quantum Cryptography (PQC) algorithms are currently being standardised and their early implementations are not as efficient as the well-established public key cryptography (PKC) algorithms that have benefited from decades of optimisations. We ...

Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular ...

The bottleneck between the processor and memory is the most significant barrier to the ongoing development of efficient processing systems. Therefore, a research effort begun to shift from processor-centric architectures to memory-...

• A hardware/software co-design flow specific to associative in-memory processors.

Remote firmware updates have become the de facto standard to guarantee a secure deployment of often decentrally operated IoT devices. However, the transfer and the provision of updates are considered as highly security-critical. Immunity ...

High-level synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit of this approach is that ever-increasing system-on-chip (SoC) ...

OFDM (Orthogonal frequency division multiplexing) is an efficient modulation scheme for wide-band digital communications and applications ranging from modems to next-generation high-speed wireless data communications[9]. Several enhancements of the OFDM ...

Reconstructive signal processing algorithms encompass a broad spectrum of computational methods. Fortunately, most of the methods fall into the classes of the matrix algebraic calculations, convolution, or transform type algorithms. These algorithms ...

This paper presents the development and modeling of a discrete cosine transform (DCT) algorithm using SystemC. The DCT algorithm is necessary to implement the signal compression subsystem for an ambulatory EEG system. Hardware/Software co-design ...

We propose an algorithm for assessing probabilistic timing constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of such constraints, as this has the potential for ...

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which ...

This paper presents the underlying methodology of Cosmos, an interactive approach for hardware/software co-design capable of handling multiprocessor systems and distributed architectures. The approach covers the co-design process through a set of user ...

The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardware and software cost. We consider minimization of communication cost and ...