research-article

Analytical Estimation of Vector Access Performance in Parallel Memory Architectures

Authors:

D. T. Harper, III,

Y. CostaAuthors Info & Claims

IEEE Transactions on Computers, Volume 42, Issue 5

Pages 616 - 624

https://doi.org/10.1109/12.223682

Published: 01 May 1993 Publication History

Abstract

A limiting factor in high-performance vector computers is the rate at which data can be moved to and from memory during vector loads and stores. To increase the bandwidth of vector memory operations, several investigators have proposed the use of noninterleaved storage mappings, also known as storage schemes. A method of analyzing the performance of vector references for the class of storage schemes referred to as XOR schemes is described. The proposed measure of relative performance, the variability of an access, is defined and its computation is outlined. The use of variability as a performance indicator is demonstrated and compared with performance measurements made using simulation. One of the key aspects of the variability measure is its capability to lend insight to the transient behavior of vector accesses.

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{4} D. T. Harper III and J. R. Jump, "Vector access performance in parallel memories using a skewed storage scheme," IEEE Trans. Comput., vol. C-36, no. 12, pp. 1440-1449, 1987.

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{5} J. Frailong, W. Jalby, and J. Lenfant, "XOR-Schemes: A flexible data organization in parallel memories," in Proc. Int. Conf. Parallel Processing, 1985, pp. 276-283.

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{11} D. T. Harper III, "Block, multistride vector, and FFT accesses in parallel memory systems," IEEE Trans. Parallel Distributed Syst., vol. 2, pp. 43-51, Jan. 1991.

Digital Library

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Cited By

Blelloch GGibbons PMatias YZagha M(1997)Accounting for Memory Bank Contention and Delay in High-Bandwidth MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6154408:9(943-958)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/71.615440
Phalke VGopinath B(1997)Compression-Based Program Characterization for Improving Cache Memory PerformanceIEEE Transactions on Computers10.1109/12.64429246:11(1174-1186)Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.1109/12.644292
Jorda JMzoughi ALitaize DValero M(1995)Semi-linear and bi-base storage schemes classesProceedings of the 9th international conference on Supercomputing10.1145/224538.224574(299-307)Online publication date: 3-Jul-1995
https://dl.acm.org/doi/10.1145/224538.224574
Show More Cited By

Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
1. General and reference
  1. Cross-computing tools and techniques

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 42, Issue 5

May 1993

134 pages

ISSN:0018-9340

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Copyright © Copyright © 1993 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 May 1993

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Cited By

Blelloch GGibbons PMatias YZagha M(1997)Accounting for Memory Bank Contention and Delay in High-Bandwidth MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6154408:9(943-958)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/71.615440
Phalke VGopinath B(1997)Compression-Based Program Characterization for Improving Cache Memory PerformanceIEEE Transactions on Computers10.1109/12.64429246:11(1174-1186)Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.1109/12.644292
Jorda JMzoughi ALitaize DValero M(1995)Semi-linear and bi-base storage schemes classesProceedings of the 9th international conference on Supercomputing10.1145/224538.224574(299-307)Online publication date: 3-Jul-1995
https://dl.acm.org/doi/10.1145/224538.224574
Blelloch GGibbons PMatias YZagha MLeiserson C(1995)Accounting for memory bank contention and delay in high-bandwidth multiprocessorsProceedings of the seventh annual ACM symposium on Parallel algorithms and architectures10.1145/215399.215425(84-94)Online publication date: 20-Jul-1995
https://dl.acm.org/doi/10.1145/215399.215425
Kurian LChoi BHulina PCoraor L(1994)Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved MemoriesProceedings of the 1994 International Conference on Parallel Processing - Volume 0110.1109/ICPP.1994.130(212-219)Online publication date: 15-Aug-1994
https://dl.acm.org/doi/10.1109/ICPP.1994.130

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